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• a7870b87eb project: more cleanup master project-1 CaZzzer 2024-11-23 22:22:12 -08:00
• 0361dcc161 project: some cleanup CaZzzer 2024-11-20 01:30:47 -08:00
• ceba9d6fd5 control unit: fix jal, add comprehensive instruction test CaZzzer 2024-11-20 00:52:11 -08:00
• 0198e8be41 control unit: fix stack pointer inc/dec, passing SP15, FL15, RevFib CaZzzer 2024-11-18 23:00:06 -08:00
• 507fa2e863 control unit: passing SP15 and SP17 CaZzzer 2024-11-18 22:18:26 -08:00
• b651f04748 control unit: more progress, fibonacci working CaZzzer 2024-11-18 00:47:16 -08:00
• 2ffd8c9424 da vinci tb: patch for smaller (20-bit) memory for faster tests CaZzzer 2024-11-18 00:46:22 -08:00
• 05c950a0f8 control unit: progress CaZzzer 2024-11-17 04:19:03 -08:00
• 5d64b65212 data path: replace instruction register with D-latch CaZzzer 2024-11-17 02:38:11 -08:00
• 9e6d1d5df2 control unit: ctrl signal refactor CaZzzer 2024-11-17 02:30:25 -08:00
• 1e1d0f0e05 project: track output CaZzzer 2024-11-17 01:14:29 -08:00
• 8810726d65 project: minor refactors CaZzzer 2024-11-17 00:42:38 -08:00
• c8baf4262a project: edit ctrl signal to match doc CaZzzer 2024-11-16 23:54:09 -08:00
• 02781c283f project: add da vinci test programs CaZzzer 2024-11-12 19:26:45 -08:00
• 88b635122f (WIP) control unit: initial implementation of things CaZzzer 2024-11-12 18:02:06 -08:00
• d10a3d6130 data path: fix port connection warnings project CaZzzer 2024-11-12 01:49:30 -08:00
• a2d547df45 data path: initial gate level implementation CaZzzer 2024-11-12 01:49:30 -08:00
• ff1c1630b2 data path: add initial wires and buffers CaZzzer 2024-11-12 00:20:29 -08:00
• ff6e7792f4 misc: fix unconnected port warnings for ALU and TWOSCOMP CaZzzer 2024-11-12 13:08:35 -08:00
• 9584db84fd logic: add 32-bit register with parameterized preset pattern CaZzzer 2024-11-12 00:24:41 -08:00
• dbc23d80e4 lab-08: fix register file - disable writing when WRITE=0 CaZzzer 2024-10-24 23:11:59 -07:00
• c3da7787d3 lab-08: fix HiZ on register file when READ=0 CaZzzer 2024-10-21 20:25:05 -07:00
• 171a6d1f77 lab-08: fix HiZ on register file when READ=0 lab-08 CaZzzer 2024-10-24 12:33:13 -07:00
• 3835618ef9 (WIP) lab-08: Testbentch for HiZ on register file READ=0 CaZzzer 2024-10-22 12:40:00 -07:00
• b00650f91b (WIP) lab-08: High Z for register file READ=0 CaZzzer 2024-10-21 20:25:05 -07:00
• eca53c1104 lab-08: gate level model for 32x32-bit register file lab-08-rebase CaZzzer 2024-10-19 18:28:15 -07:00
• 3091103f81 lab-07: gate level model for 32-bit register CaZzzer 2024-10-19 16:05:17 -07:00
• cce0c524d9 lab-06: gate level model for Arithmetic & Logic Unit CaZzzer 2024-10-10 18:59:09 -07:00
• 1ab4ea027d lab-05: gate level model for 32-bit barrel shifter CaZzzer 2024-10-10 13:31:00 -07:00
• 5a4b5a312a lab-04: gate level model for 32-bit signed multiplier CaZzzer 2024-10-08 00:05:19 -07:00
• a125ae533b lab-08: gate level model for 32x32-bit register file CaZzzer 2024-10-19 18:28:15 -07:00
• 2d6ec06741 (WIP) lab-08: Register File CaZzzer 2024-10-19 17:23:04 -07:00
• 7e4a63e155 (WIP) lab-08: Decoder_5x32, Mux32_32x1 CaZzzer 2024-10-19 16:51:30 -07:00
• 41ecb62082 lab-07: gate level model for 32-bit register lab-07 CaZzzer 2024-10-19 16:05:17 -07:00
• a110f7c042 (WIP): REG1 CaZzzer 2024-10-19 15:54:51 -07:00
• 7c0645eaa1 (WIP): D Latch and D FlipFlop CaZzzer 2024-10-19 15:47:35 -07:00
• d217faf166 (WIP): SR Latch CaZzzer 2024-10-19 15:20:23 -07:00
• 7bb0331226 WIP: failed attempt to use many-input or gates lab-06 CaZzzer 2024-10-19 15:18:51 -07:00
• 8dbdebb9ce lab-06: gate level model for Arithmetic & Logic Unit CaZzzer 2024-10-10 18:59:09 -07:00
• 800b80ef85 lab-06 (WIP): mux32_16x1 working CaZzzer 2024-10-10 15:14:25 -07:00
• 585d9713d2 lab-05: gate level model for 32-bit barrel shifter lab-05 CaZzzer 2024-10-10 13:31:00 -07:00
• cdfaa51626 lab-04: signed mult working lab-04 CaZzzer 2024-10-08 16:00:01 -07:00
• 73aa647c9b lab-04 (WIP): unsigned mult working CaZzzer 2024-10-08 14:48:44 -07:00
• 6fa94cfe59 lab-04 (WIP): mux implementation CaZzzer 2024-10-08 00:05:19 -07:00
• 597e245641 lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement CaZzzer 2024-10-02 16:18:00 -07:00
• 42732e4fe0 lab-02: gate level model for ripple carry adder subtractor CaZzzer 2024-10-01 11:01:17 -07:00
• f4a3e3bb8b lab-03: clean up twos complement modules lab-03 CaZzzer 2024-10-03 21:14:33 -07:00
• f5b19ae9fc lab-02: fix behavioral xor statement in RC_ADD_SUB modules CaZzzer 2024-10-03 20:25:36 -07:00
• 48bdad0e8b lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement CaZzzer 2024-10-03 20:21:30 -07:00
• bb7e172316 implement a Verilog gate level model for 64-bit Ripple Carry Adder and 32/64-bit twos complement CaZzzer 2024-10-02 16:18:00 -07:00
• 3801d523de implement a Verilog gate level model for ripple carry adder subtractor lab-02 CaZzzer 2024-10-01 20:42:02 -07:00
• d1475b5a4f implement a Verilog gate level model for ripple carry adder subtractor CaZzzer 2024-10-01 11:01:17 -07:00
• 87e48f162e implement a Verilog gate level model for 32-bit basic logic gates CaZzzer 2024-10-01 10:44:45 -07:00
• 5520d6d716 initial commit CaZzzer 2024-10-01 10:39:56 -07:00