CaZzzer/cs147dv
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Yuri Tatishchev a7870b87eb
project: more cleanup
2024-11-24 01:14:12 -08:00
DOC
initial commit
2024-10-01 10:39:56 -07:00
GOLDEN
project: add da vinci test programs
2024-11-16 16:49:44 -08:00
OUTPUT
control unit: fix jal, add comprehensive instruction test
2024-11-20 00:55:20 -08:00
TESTBENCH
project: more cleanup
2024-11-24 01:14:12 -08:00
TESTPROGRAM
control unit: fix jal, add comprehensive instruction test
2024-11-20 00:55:20 -08:00
.gitignore
project: add da vinci test programs
2024-11-16 16:49:44 -08:00
alu.v
misc: fix unconnected port warnings for ALU and TWOSCOMP
2024-11-12 13:11:48 -08:00
barrel_shifter.v
lab-05: gate level model for 32-bit barrel shifter
2024-10-19 18:39:16 -07:00
clk_gen.v
initial commit
2024-10-01 10:39:56 -07:00
control_unit.v
project: more cleanup
2024-11-24 01:14:12 -08:00
da_vinci.v
initial commit
2024-10-01 10:39:56 -07:00
data_path.v
project: some cleanup
2024-11-20 02:01:20 -08:00
full_adder.v
lab-02: gate level model for ripple carry adder subtractor
2024-10-03 21:30:09 -07:00
half_adder.v
lab-02: gate level model for ripple carry adder subtractor
2024-10-03 21:30:09 -07:00
logic_32_bit.v
lab-04: gate level model for 32-bit signed multiplier
2024-10-19 18:39:02 -07:00
logic.v
data path: replace instruction register with D-latch
2024-11-17 02:38:11 -08:00
memory.v
initial commit
2024-10-01 10:39:56 -07:00
mult.v
lab-04: gate level model for 32-bit signed multiplier
2024-10-19 18:39:02 -07:00
mux.v
lab-07: gate level model for 32-bit register
2024-10-19 18:39:30 -07:00
prj_definition.v
da vinci tb: patch for smaller (20-bit) memory for faster tests
2024-11-18 00:46:22 -08:00
processor.v
initial commit
2024-10-01 10:39:56 -07:00
rc_add_sub_32.v
lab-02: gate level model for ripple carry adder subtractor
2024-10-03 21:30:09 -07:00
register_file.v
lab-08: fix register file - disable writing when WRITE=0
2024-10-24 23:11:59 -07:00
Description
CS147DV instruction set implementation in Verilog
348 KiB
Languages
Verilog 96%
Coq 4%