lab-05: gate level model for 32-bit barrel shifter

Gate level implementation for the following components:
- SHIFT32_L
- SHIFT32_R
- BARREL_SHIFTER32
- SHIFT32

barrel_shifter.v

@@ -21,7 +21,21 @@ input [31:0] D;
 input [31:0] S;
 input LnR;
 
-// TBD
+// check if upper bits are nonzero
+wire oob [31:5];
+buf (oob[5], S[5]);
+genvar i;
+generate
+    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
+        or (oob[i], oob[i-1], S[i]);
+    end
+endgenerate
+
+wire [31:0] shifted;
+BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
+
+// return 0 if S >= 32
+MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
 
 endmodule
 
@@ -34,7 +48,11 @@ input [31:0] D;
 input [4:0] S;
 input LnR;
 
-// TBD
+wire [31:0] shifters [1:0];
+SHIFT32_R shifter_r(shifters[0], D, S);
+SHIFT32_L shifter_l(shifters[1], D, S);
+
+MUX32_2x1 mux_lnr(Y, shifters[0], shifters[1], LnR);
 
 endmodule
 
@@ -46,7 +64,22 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-// TBD
+wire [31:0] stages [5:0];
+buf stage0[31:0] (stages[0], D);
+
+genvar i, j;
+generate
+    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
+        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
+            if (j < 32 - (2 ** i))
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j + (2 ** i)], S[i]);
+            else
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
+        end
+    end
+endgenerate
+
+buf out[31:0] (Y, stages[5]);
 
 endmodule
 
@@ -58,7 +91,22 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-// TBD
+
+wire [31:0] stages [5:0];
+buf stage0[31:0] (stages[0], D);
+
+genvar i, j;
+generate
+    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
+        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
+            if (j >= (2 ** i))
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j - (2 ** i)], S[i]);
+            else
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
+        end
+    end
+endgenerate
+
+buf out[31:0] (Y, stages[5]);
 
 endmodule
-

logic.v

@@ -141,6 +141,12 @@ output [3:0] D;
 // input
 input [1:0] I;
 
-// TBD
+wire I_not [1:0];
+not I_inv[1:0] (I_not, I);
+
+and (D[0], I_not[1], I_not[0]);
+and (D[1], I_not[1], I[0]);
+and (D[2], I[1], I_not[0]);
+and (D[3], I[1], I[0]);
 
 endmodule

mux.v

@@ -55,7 +55,11 @@ input [31:0] I14;
 input [31:0] I15;
 input [3:0] S;
 
-// TBD
+
+wire [31:0] x0, x1;
+MUX32_8x1 mux8_0(x0, I0, I1, I2, I3, I4, I5, I6, I7, S[2:0]);
+MUX32_8x1 mux8_1(x1, I8, I9, I10, I11, I12, I13, I14, I15, S[2:0]);
+MUX32_2x1 out(Y, x0, x1, S[3]);
 
 endmodule
 
@@ -74,7 +78,10 @@ input [31:0] I6;
 input [31:0] I7;
 input [2:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_4x1 mux4_0(x0, I0, I1, I2, I3, S[1:0]);
+MUX32_4x1 mux4_1(x1, I4, I5, I6, I7, S[1:0]);
+MUX32_2x1 out(Y, x0, x1, S[2]);
 
 endmodule
 
@@ -89,7 +96,31 @@ input [31:0] I2;
 input [31:0] I3;
 input [1:0] S;
 
-// TBD
+// wire [3:0] x;
+// DECODER_2x4 d(x, S);
+//
+// genvar i;
+// generate
+//     for (i = 0; i < 32; i = i + 1) begin : mux32_4x1_gen
+//         // enabling circuit
+//         wire [3:0] o;
+//         and and0_inst(o[0], x[0], I0[i]);
+//         and and1_inst(o[1], x[1], I1[i]);
+//         and and2_inst(o[2], x[2], I2[i]);
+//         and and3_inst(o[3], x[3], I3[i]);
+//
+//         // combining gate
+//         wire [1:0] p;
+//         or or0(p[0], o[0], o[1]);
+//         or or1(p[1], o[2], o[3]);
+//         or out(Y[i], p[0], p[1]);
+//     end
+// endgenerate
+
+wire [31:0] x0, x1;
+MUX32_2x1 mux2_0(x0, I0, I1, S[0]);
+MUX32_2x1 mux2_1(x1, I2, I3, S[0]);
+MUX32_2x1 out(Y, x0, x1, S[1]);
 
 endmodule
 
@@ -103,17 +134,19 @@ input [31:0] I1;
 input S;
 
 // only need 1 not gate
+wire S_not;
 not (S_not, S);
 
-wire [31:0] x0, x1;
+// wire [31:0] x0, x1;
 
 genvar i;
 generate
     for (i = 0; i < 32; i = i + 1)
     begin : mux32_gen_loop
-        and (x0[i], S_not, I0[i]);
-        and (x1[i], S, I1[i]);
-        or (Y[i], x0[i], x1[i]);
+        wire x0, x1;
+        and (x0, S_not, I0[i]);
+        and (x1, S, I1[i]);
+        or (Y[i], x0, x1);
     end
 endgenerate
 
@@ -126,6 +159,7 @@ output Y;
 //input list
 input I0, I1, S;
 
+wire S_not, x0, x1;
 not (S_not, S);
 and (x0, S_not, I0);
 and (x1, S, I1);