lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-// TBD
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -31,7 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-// TBD
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -143,4 +143,4 @@ input [1:0] I;
 
 // TBD
 
-endmodule
+endmodule