CaZzzer f4a3e3bb8b lab-03: clean up twos complement modules

2024-10-03 21:14:33 -07:00

DOC

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GOLDEN

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TESTBENCH

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.gitignore

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alu.v

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barrel_shifter.v

initial commit

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clk_gen.v

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control_unit.v

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da_vinci.v

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data_path.v

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full_adder.v

implement a Verilog gate level model for ripple carry adder subtractor

2024-10-01 20:42:02 -07:00

half_adder.v

implement a Verilog gate level model for ripple carry adder subtractor

2024-10-01 20:42:02 -07:00

logic_32_bit.v

implement a Verilog gate level model for 32-bit basic logic gates

2024-10-01 10:44:45 -07:00

logic.v

lab-03: clean up twos complement modules

2024-10-03 21:14:33 -07:00

memory.v

initial commit

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mult.v

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mux.v

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prj_definition.v

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processor.v

initial commit

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rc_add_sub_32.v

lab-02: fix behavioral xor statement in RC_ADD_SUB modules

2024-10-03 20:25:36 -07:00

register_file.v

initial commit

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S

Description

CS147DV instruction set implementation in Verilog

348 KiB

Languages

Verilog 96%

Coq 4%