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(WIP) lab-08: Decoder_5x32, Mux32_32x1

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This commit is contained in:
Yuri Tatishchev 2024-10-19 16:51:30 -07:00
parent 41ecb62082
commit 7e4a63e155
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
2 changed files with 48 additions and 4 deletions
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41
logic.v
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@ -127,7 +127,19 @@ output [31:0] D;
// input
input [4:0] I;
// TBD
wire [15:0] half;
wire I_not;
not I_inv(I_not, I[4]);
DECODER_4x16 d(half, I[3:0]);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : d5_gen
and msb0(D[i], I_not, half[i]);
and msb1(D[i + 16], I[4], half[i]);
end
endgenerate
endmodule
@ -138,7 +150,19 @@ output [15:0] D;
// input
input [3:0] I;
// TBD
wire [7:0] half;
wire I_not;
not I_inv(I_not, I[3]);
DECODER_3x8 d(half, I[2:0]);
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : d4_gen
and msb0(D[i], I_not, half[i]);
and msb1(D[i + 8], I[3], half[i]);
end
endgenerate
endmodule
@ -150,8 +174,19 @@ output [7:0] D;
// input
input [2:0] I;
//TBD
wire [3:0] half;
wire I_not;
not I_inv(I_not, I[2]);
DECODER_2x4 d(half, I[1:0]);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : d3_gen
and msb0(D[i], I_not, half[i]);
and msb1(D[i + 4], I[2], half[i]);
end
endgenerate
endmodule

11
mux.v
View File

@ -27,7 +27,16 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
input [4:0] S;
// TBD
wire [31:0] x0, x1;
MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
I8, I9, I10, I11, I12, I13, I14, I15,
S[3:0]
);
MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
I24, I25, I26, I27, I28, I29, I30, I31,
S[3:0]
);
MUX32_2x1 out(Y, x0, x1, S[4]);
endmodule