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This commit is contained in:
Iurii Tatishchev 2024-10-01 10:39:56 -07:00
commit 5520d6d716
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
54 changed files with 2855 additions and 0 deletions
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29
.gitignore vendored Normal file
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# Created by https://www.toptal.com/developers/gitignore/api/modelsim
# Edit at https://www.toptal.com/developers/gitignore?templates=modelsim
### ModelSim ###
# ignore ModelSim generated files and directories (temp files and so on)
[_@]*
# ignore compilation output of ModelSim
*.mti
*.dat
*.dbs
*.psm
*.bak
*.cmp
*.jpg
*.html
*.bsf
# ignore simulation output of ModelSim
wlf*
*.wlf
*.vstf
*.ucdb
cov*/
transcript*
sc_dpiheader.h
vsim.dbg
# End of https://www.toptal.com/developers/gitignore/api/modelsim

BIN
DOC/proj_02_guideline.pdf Normal file
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Binary file not shown.

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GOLDEN/AND32_2x1_TB.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/AND32_2x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
ffff0000
0000ffff

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GOLDEN/INV32_1x1_TB.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/INV32_1x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000ffff
ffffffff
5a5a5a5a
0000ffff
ffff0000

8
GOLDEN/NOR32_2x1_TB.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/NOR32_2x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
ffffffff
00000000
0000ffff
ffff0000

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GOLDEN/OR32_2x1_TB.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/OR32_2x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
ffffffff
00000000
ffffffff
ffff0000
0000ffff

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GOLDEN/alu_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/ALU_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000014
00000000
00000000
00000001
00000064
00000000
00000000
00000001
00002800
00000000
0000000a
00000000
0000000a
00000000
fffffff5
00000000
00000000
00000001
00000000
00000001
ffffffe2
00000000
ffffff1f
00000000
0001ffff
00000000
fff88000
00000000
00000001
00000000
ffffffff
00000000
00000000
00000001
00000001
00000000
00000000
00000001
00000032
00000000
fffffd8f
00000000
00000000
00000001
00000000
00000001
00000001
00000000
ffffffff
00000000
00000000
00000001
00000000
00000001
ffffffc4
00000000
00000000
00000001
00000384
00000000
00000000
00000001
00000000
00000001
ffffffe2
00000000
ffffffe2
00000000
0000001d
00000000
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
ffffffff
00000000
00000000
00000001
0000001b
00000000
ffffffc7
00000000
fffffd8a
00000000
00000000
00000001
00000000
00000001
00000020
00000000
fffffffb
00000000
00000004
00000000
00000001
00000000
00000017
00000000
00000017
00000000
00000000
00000001
00000017
00000000
00000017
00000000
00000000
00000001
00000017
00000000
ffffffe8
00000000
00000000
00000001
00000046
00000000
ffffffba
00000000
00000000
00000001
00000000
00000001
00000000
00000001
00000000
00000001
00000046
00000000
ffffffb9
00000000
00000001
00000000

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GOLDEN/barret_shifter_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/BARREL_SHIFTER32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
4b4b4b4a
96969694
2d2d2d28
5a5a5a50
b4b4b4a0
69696940
d2d2d280
a5a5a500
4b4b4a00
96969400
2d2d2800
5a5a5000
b4b4a000
69694000
d2d28000
a5a50000
4b4a0000
96940000
2d280000
5a500000
b4a00000
69400000
d2800000
a5000000
4a000000
94000000
28000000
50000000
a0000000
40000000
80000000
00000000
52d2d2d2
29696969
14b4b4b4
0a5a5a5a
052d2d2d
02969696
014b4b4b
00a5a5a5
0052d2d2
00296969
0014b4b4
000a5a5a
00052d2d
00029696
00014b4b
0000a5a5
000052d2
00002969
000014b4
00000a5a
0000052d
00000296
0000014b
000000a5
00000052
00000029
00000014
0000000a
00000005
00000002
00000001
00000000

10
GOLDEN/d_ff_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/D_FF_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000012
00000013
0000000b
00000017
0000000d
0000000f
00000017

11
GOLDEN/d_latch_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/D_LATCH_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000022
00000023
00000027
00000011
00000013
00000017
0000002f
0000001b

10
GOLDEN/d_reg1_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/REG1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000022
00000023
0000000b
0000002f
0000001d
0000001f
00000023

11
GOLDEN/d_reg32_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/REG32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
a5a5a5a5
ffff0000
00000000
00000000
0000ffff
0000ffff

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GOLDEN/decoder_5x32_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/DECODER_5x32_TB/result
// format=bin addressradix=h dataradix=b version=1.0 wordsperline=1 noaddress
00000000000000000000000000000001
00000000000000000000000000000010
00000000000000000000000000000100
00000000000000000000000000001000
00000000000000000000000000010000
00000000000000000000000000100000
00000000000000000000000001000000
00000000000000000000000010000000
00000000000000000000000100000000
00000000000000000000001000000000
00000000000000000000010000000000
00000000000000000000100000000000
00000000000000000001000000000000
00000000000000000010000000000000
00000000000000000100000000000000
00000000000000001000000000000000
00000000000000010000000000000000
00000000000000100000000000000000
00000000000001000000000000000000
00000000000010000000000000000000
00000000000100000000000000000000
00000000001000000000000000000000
00000000010000000000000000000000
00000000100000000000000000000000
00000001000000000000000000000000
00000010000000000000000000000000
00000100000000000000000000000000
00001000000000000000000000000000
00010000000000000000000000000000
00100000000000000000000000000000
01000000000000000000000000000000
10000000000000000000000000000000

11
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// memory data file (do not edit the following line - required for mem load use)
// instance=/FULL_ADDER_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000001
00000002
00000001
00000002
00000002
00000003

7
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// memory data file (do not edit the following line - required for mem load use)
// instance=/HALF_ADDER_TB/results
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000001
00000002

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GOLDEN/mult32_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/MULT_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000000000c8
000000000000002d
ffffffffffffff90
ffffffffffffff42
3100000000000000
cf00000000000000
cf00000000000000
3100000000000000

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GOLDEN/mult32_u_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/MULT_U_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000000000c8
000000000000002d
0000000000000070
00000000000000be
3100000000000000

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// memory data file (do not edit the following line - required for mem load use)
// instance=/MUX32_16x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007
00000008
00000009
0000000a
0000000b
0000000c
0000000d
0000000e
0000000f

5
GOLDEN/mux32_2x1_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/MUX32_2x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
a5a5a5a5
5a5a5a5a

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GOLDEN/mux32_32x1_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/MUX32_32x1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007
00000008
00000009
0000000a
0000000b
0000000c
0000000d
0000000e
0000000f
00000010
00000011
00000012
00000013
00000014
00000015
00000016
00000017
00000018
00000019
0000001a
0000001b
0000001c
0000001d
0000001e
0000001f

8
GOLDEN/rc_add_sub_32.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/RC_ADD_SUB_32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000001e
fffffff6
00000003
00000004
00005555

67
GOLDEN/rf_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/RF_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000001
00000001
00000002
00000002
00000003
00000003
00000004
00000004
00000005
00000005
00000006
00000006
00000007
00000007
00000008
00000008
00000009
00000009
0000000a
0000000a
0000000b
0000000b
0000000c
0000000c
0000000d
0000000d
0000000e
0000000e
0000000f
0000000f
00000010
00000010
00000011
00000011
00000012
00000012
00000013
00000013
00000014
00000014
00000015
00000015
00000016
00000016
00000017
00000017
00000018
00000018
00000019
00000019
0000001a
0000001a
0000001b
0000001b
0000001c
0000001c
0000001d
0000001d
0000001e
0000001e
0000001f
0000001f

17
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// memory data file (do not edit the following line - required for mem load use)
// instance=/SR_LATCH_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000042
00000043
00000047
0000004b
0000004f
00000021
00000023
00000027
0000002b
0000002f
0000005b
00000053
00000037
00000033

5
GOLDEN/twoscomp32_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/TWOSCOMP32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
fffffff6
00000005

5
GOLDEN/twoscomp64_tb.out.golden Normal file
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// memory data file (do not edit the following line - required for mem load use)
// instance=/TWOSCOMP64_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
fffffffffffffff6
0000000000000005

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// Name: alu_tb.v
// Module: ALU_TB
//
// Notes: - Testbench for ALU
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module ALU_TB;
// reg list
reg [`DATA_INDEX_LIMIT:0] OP1; // operand 1
reg [`DATA_INDEX_LIMIT:0] OP2; // operand 2
reg [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
// output list
wire [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
wire ZERO;
// results
integer ridx;
reg [`DATA_INDEX_LIMIT:0] result[199:0];
// Testcases
integer oprnd_idx, oprn_idx;
integer NumSet01[0:7];
integer NumSet02[0:7];
integer OpCode[0:8];
ALU alu_inst(.OUT(OUT), .ZERO(ZERO), .OP1(OP1), .OP2(OP2), .OPRN(OPRN));
initial
begin
// Initialize number sets
NumSet01[0] = 10; NumSet01[1] = -15; NumSet01[2] = 25; NumSet01[3] = -30; NumSet01[4] = 0; NumSet01[5] = -15; NumSet01[6] = 23; NumSet01[7] = 0;
NumSet02[0] = 10; NumSet02[1] = 15; NumSet02[2] = -25; NumSet02[3] = -30; NumSet02[4] = 0; NumSet02[5] = 42; NumSet02[6] = 0; NumSet02[7] = 70;
ridx = 0;
// Set of operation
OpCode[0] = 1; // add
OpCode[1] = 2; // sub
OpCode[2] = 3; // mult
OpCode[3] = 4; // shiftR
OpCode[4] = 5; // shiftL
OpCode[5] = 6; // and
OpCode[6] = 7; // or
OpCode[7] = 8; // nor
OpCode[8] = 9; // slt
// Loop through operands and operation
for(oprnd_idx=0; oprnd_idx<8; oprnd_idx=oprnd_idx+1)
begin
for(oprn_idx=0; oprn_idx<9; oprn_idx=oprn_idx+1)
begin
#1 OP1=NumSet01[oprnd_idx]; OP2=NumSet02[oprnd_idx]; OPRN=OpCode[oprn_idx];
#1
$write("===> %0d ",$signed(OP1));
case(OPRN)
1: $write("+");
2: $write("-");
3: $write("*");
4: $write(">>");
5: $write("<<");
6: $write("&");
7: $write("|");
8: $write("|~");
9: $write("slt");
endcase
$write(" %0d = %0d [%d]\n", $signed(OP2), $signed(OUT), ZERO);
result[ridx] = OUT; ridx = ridx + 1;
result[ridx] = ZERO; ridx = ridx + 1;
end
end
#1
$writememh("./OUTPUT/alu_tb.out", result, 0, (ridx-1));
$stop;
end
endmodule

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TESTBENCH/barrel_shifter_tb.v Normal file
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// Name: barrel_shifter_tb.v
// Module: BARREL_SHIFTER32_TB
//
// Notes: - Testbench for shift module
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module BARREL_SHIFTER32_TB;
reg [31:0] D;
reg [31:0] S;
reg LnR;
wire [31:0] Y;
integer reg_idx;
reg [`DATA_INDEX_LIMIT:0] result[0:63];
integer i, e;
integer no_of_test=0;
integer no_of_pass=0;
SHIFT32 shift_inst(.Y(Y), .D(D), .S(S), .LnR(LnR));
initial
begin
reg_idx=0;
D=32'ha5a5a5a5;
S=32'h00000000;
LnR=1'b1; // left shift
for(i=1; i<33; i=i+1)
begin
#5
no_of_test = no_of_test + 1;
S=i;
e = D << S;
#5
if (e !== Y)
begin
$write("[TEST %2d] (%8x << %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
end
else
no_of_pass = no_of_pass + 1;
result[reg_idx] = Y; reg_idx=reg_idx+1;
end
#5 LnR=1'b0; // right shift
for(i=1; i<33; i=i+1)
begin
#5
no_of_test = no_of_test + 1;
S=i;
e = D >> S;
#5
if (e !== Y)
begin
$write("[TEST %2d] (%8x >> %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
end
else
no_of_pass = no_of_pass + 1;
result[reg_idx] = Y; reg_idx=reg_idx+1;
end
$write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/barret_shifter_tb.out",result);
$stop;
end
endmodule

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// Name: da_vinci_tb.v
// Module: DA_VINCI_TB
//
// Outputs are for testbench observations only
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for DA_VINCI system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module DA_VINCI_TB;
// output list
wire [`ADDRESS_INDEX_LIMIT:0] ADDR;
wire READ, WRITE, CLK;
// inout list
wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
// reset
reg RST;
integer t1=1, t2=1, t3=1, t4=1, t5=1;
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// DA_VINCI v1.0 instance
defparam da_vinci_inst.mem_init_file = "./TESTPROGRAM/fibonacci.dat";
//defparam da_vinci_inst.mem_init_file = "RevFib.dat";
DA_VINCI da_vinci_inst(.MEM_DATA_OUT(MEM_DATA_OUT),
.MEM_DATA_IN(MEM_DATA_IN),
.ADDR(ADDR), .READ(READ),
.WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
RST=1'b1;
if (t1 === 1)
begin
/* START : test 1*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating fibonacci.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/fibonacci.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating fibonacci.dat\n", "");
$write("\n");
$writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01000000, 'h0100000f);
/* END : test 1*/
end
if (t2 === 1)
begin
/* START : test 2*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating RevFib.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/RevFib.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating RevFib.dat\n", "");
$write("\n");
$writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff0, 'h03ffffff);
/* END : test 2*/
end
if (t3 === 1)
begin
/* START : test 3*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_SP17_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h0100800A);
/* END : test 3*/
end
if (t4 === 1)
begin
/* START : test 4*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_FL15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#6000 $write("\n");
$write("===> Done simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff6, 'h03ffffff);
/* END : test 4*/
end
if (t5 === 1)
begin
/* START : test 5*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_SP15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h01008005);
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffffA, 'h03ffffff);
/* END : test 5*/
end
$stop;
end
endmodule;

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// Name: full_adder_tb.v
// Module: FULL_ADDER_TB
//
// Notes: - Testbench for full adder
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module FULL_ADDER_TB;
reg A, B, CI;
wire S, CO;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
integer i;
FULL_ADDER fa_inst(.S(S), .CO(CO), .A(A), .B(B), .CI(CI));
initial
begin
A=0; B=0; CI=0;
#1 result[0] = 32'h00000000 | {CO,S};
for(i=1; i<8; i=i+1)
begin
#1 CI=i[2]; A=i[1]; B=i[0];
#1 result[i] = 32'h00000000 | {CO,S};
end
#1
$writememh("./OUTPUT/full_adder.out",result);
$stop;
end
endmodule

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// Name: half_adder_tb.v
// Module: HALF_ADDER_TB
//
// Notes: - Testbench for half adder
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module HALF_ADDER_TB;
reg A, B;
wire Y, C;
reg [`DATA_INDEX_LIMIT:0] results[0:3];
HALF_ADDER ha_inst(.Y(Y), .C(C), .A(A), .B(B));
initial
begin
A=1'b0; B=1'b0;
#1 results[0] = 32'h00000000 | {C,Y};
#1 A=1'b0; B=1'b1;
#1 results[1] = 32'h00000000 | {C,Y};
#1 A=1'b1; B=1'b0;
#1 results[2] = 32'h00000000 | {C,Y};
#1 A=1'b1; B=1'b1;
#1 results[3] = 32'h00000000 | {C,Y};
#5
$writememh("./OUTPUT/half_adder.out",results,0,3);
$stop;
end
endmodule

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// Name: logic_32_bit_tb.v
// Module: NOR32_2x1_TB
// AND32_2x1_TB
// INV32_1x1_TB
// OR32_2x1_TB
//
// Notes: - Testbench for shift module
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module NOR32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
NOR32_2x1 nor32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/NOR32_2x1_TB.out",result);
$stop;
end
endmodule
module AND32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
AND32_2x1 and32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/AND32_2x1_TB.out",result);
$stop;
end
endmodule
module INV32_1x1_TB;
//Driver
reg [31:0] A;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
INV32_1x1 inv32_1x1_inst(.Y(Y), .A(A));
initial
begin
i=0;
A=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; // Y=32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; // Y = 32'h5A5A5A5A
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/INV32_1x1_TB.out",result);
$stop;
end
endmodule
module OR32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
OR32_2x1 or32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/OR32_2x1_TB.out",result);
$stop;
end
endmodule

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// Name: logic_tb.v
// Module: TWOSCOMP32_TB,
// TWOSCOMP64_TB,
// SR_LATCH_TB,
// D_LATCH_TB,
// D_FF_PE_TB,
// REG1_TB,
// REG32_TB,
// DECODER_5x32_TB
//
// Notes: - Testbench for multiplier
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module DECODER_5x32_TB;
// observer
wire [31:0] D;
// driver
reg [4:0] I;
// result
integer i, idx;
reg [31:0] result[0:31];
DECODER_5x32 decoder_5x32_inst0(.D(D),.I(I));
initial
begin
i=0;
for(idx=0; idx<32; idx = idx + 1)
begin
#1 I=idx;
#1 result[i] = D; i=i+1;
end
#1
$writememb("./OUTPUT/decoder_5x32_tb.out",result);
$stop;
end
endmodule
module REG32_TB;
//driver
reg [`DATA_INDEX_LIMIT:0] D;
reg LOAD, RESET;
// oberver
wire [`DATA_INDEX_LIMIT:0] Q;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
REG32 reg32_inst(.Q(Q), .CLK(clk), .LOAD(LOAD), .D(D), .RESET(RESET));
initial
begin
i=0; RESET=1; D=32'ha5a5a5a5; LOAD=0;
// Reset
#1 D=32'ha5a5a5a5; LOAD=0; RESET=0;
#1 result[i] = Q; i=i+1;
// Hold
#1 D=32'ha5a5a5a5; LOAD=0; RESET=1;
#1 result[i] = Q; i=i+1;
// Normal operation
#6 D=32'ha5a5a5a5; LOAD=1; RESET=1;
#5 result[i] = Q; i=i+1;
#5 D=32'hffff0000; LOAD=1; RESET=1;
#5 result[i] = Q; i=i+1;
// Reset
#1 D=32'h0000ffff; LOAD=1; RESET=0;
#1 result[i] = Q; i=i+1;
// Normal operation
#9 D=32'h0000ffff; LOAD=1; RESET=1;
#1 result[i] = Q; i=i+1;
#10 result[i] = Q; i=i+1;
#10 D=32'h5a5a5a5a; LOAD=0; RESET=1;
#10
result[i] = Q; i=i+1;
$writememh("./OUTPUT/d_reg32_tb.out",result);
$stop;
end
endmodule
module REG1_TB;
//driver
reg D, L, nP, nR;
// oberver
wire Q,Qbar;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:6];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
REG1 reg1_inst(.Q(Q), .Qbar(Qbar), .C(clk),
.L(L), .D(D), .nP(nP), .nR(nR));
initial
begin
i=0; nP=1; nR=1; D=0; L=0;
// Preset
#1 D=0; L=0; nP=0; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Hold
#1 D=0; L=0; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Normal operation
#6 D=0; L=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#5 D=1; L=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Reset
#1 D=1; L=1; nP=1; nR=0;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Normal operation
#9 D=1; L=1; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
#10 D=0; L=0; nP=1; nR=1;
#10
result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
$writememh("./OUTPUT/d_reg1_tb.out",result);
$stop;
end
endmodule
module D_FF_TB;
//driver
reg D, nP, nR;
// oberver
wire Q,Qbar;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:6];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
D_FF d_ff_inst(.Q(Q), .Qbar(Qbar), .C(clk),
.D(D), .nP(nP), .nR(nR));
initial
begin
i=0; nP=1; nR=1; D=0;
// Preset
#1 D=0; nP=0; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Hold
#1 D=0; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Normal operation
#6 D=0; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#5 D=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Reset
#1 D=1; nP=1; nR=0;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Normal operation
#9 D=1; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#10
result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
$writememh("./OUTPUT/d_ff_tb.out",result);
$stop;
end
endmodule
module D_LATCH_TB;
// driver
reg D, C, nP, nR;
// oberver
wire Q,Qbar;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
D_LATCH d_latch_inst(.Q(Q), .Qbar(Qbar), .D(D),
.C(C), .nP(nP), .nR(nR));
initial
begin
i=0;
// Normal preset
#1 C=0; D=0; nR=1; nP=0; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Hold 1 on C=0
#1 C=0; D=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1 C=0; D=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Normal reset
#1 C=0; D=0; nR=0; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Hold 0 on C=0
#1 C=0; D=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1 C=0; D=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Set on clock
#1 C=1; D=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Reset on clock
#1 C=1; D=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1
$writememh("./OUTPUT/d_latch_tb.out",result);
$stop;
end
endmodule
module SR_LATCH_TB;
// driver
reg S, R, C, nP, nR;
// oberver
wire Q,Qbar;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:13];
SR_LATCH sr_latch_inst(.Q(Q), .Qbar(Qbar), .S(S),
.R(R), .C(C), .nP(nP), .nR(nR));
initial
begin
i=0;
// Normal reset preset
#1 C=0; S=0; R=0; nR=1; nP=0; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold 1 on C=0
#1 C=0; S=0; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=0; R=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Normal reset
#1 C=0; S=0; R=0; nR=0; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold 0 on C=0
#1 C=0; S=0; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=0; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Set on clock
#1 C=1; S=1; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold
#1 C=1; S=0; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Reset on clock
#1 C=1; S=0; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold
#1 C=1; S=0; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1
$writememh("./OUTPUT/sr_latch_tb.out",result);
$stop;
end
endmodule
module TWOSCOMP32_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
// wire
wire [`DATA_INDEX_LIMIT:0] Y;
// result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:1];
TWOSCOMP32 inst_2scomp_01(.Y(Y), .A(A));
initial
begin
i=0;
A = 10;
#1 result[i] = Y; i = i + 1;
#1 A=-5;
#1 result[i] = Y; i = i + 1;
#1
$writememh("./OUTPUT/twoscomp32_tb.out",result);
$stop;
end
endmodule
module TWOSCOMP64_TB;
// driver
reg [`DOUBLE_DATA_INDEX_LIMIT:0] A;
// wire
wire [`DOUBLE_DATA_INDEX_LIMIT:0] Y;
// result
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:1];
TWOSCOMP64 inst_2scomp_01(.Y(Y), .A(A));
initial
begin
i=0;
A = 10;
#1 result[i] = Y; i = i + 1;
#1 A=-5;
#1 result[i] = Y; i = i + 1;
#1
$writememh("./OUTPUT/twoscomp64_tb.out",result);
$stop;
end
endmodule

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// Name: proj_2_tb.v
// Module: DA_VINCI_TB
//
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for MEMORY_64MB memory system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MEM_64MB_TB;
// Storage list
reg [`ADDRESS_INDEX_LIMIT:0] ADDR;
// reset
reg READ, WRITE, RST;
// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;
// wire lists
wire CLK;
wire [`DATA_INDEX_LIMIT:0] DATA;
assign DATA = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} };
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// 64MB memory instance
defparam mem_inst.mem_init_file = "mem_content_01.dat";
MEMORY_64MB mem_inst(.DATA(DATA), .ADDR(ADDR), .READ(READ),
.WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
RST=1'b1;
READ=1'b0;
WRITE=1'b0;
DATA_REG = {`DATA_WIDTH{1'b0} };
no_of_test = 0;
no_of_pass = 0;
load_data = 'h00414020;
// Start the operation
#10 RST=1'b0;
#10 RST=1'b1;
// Write cycle
for(i=1;i<10; i = i + 1)
begin
#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR = i;
end
// Read Cycle
#10 READ=1'b0; WRITE=1'b0;
#5 no_of_test = no_of_test + 1;
if (DATA !== {`DATA_WIDTH{1'bz}})
$write("[TEST] Read %1b, Write %1b, expecting 32'hzzzzzzzz, got %8h [FAILED]\n", READ, WRITE, DATA);
else
no_of_pass = no_of_pass + 1;
// test of write data
for(i=0;i<10; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR = i;
#5 no_of_test = no_of_test + 1;
if (DATA !== i)
$write("[TEST] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", READ, WRITE, i, DATA);
else
no_of_pass = no_of_pass + 1;
end
// test for the initialize data
for(i='h001000; i<'h001010; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR = i;
#5 no_of_test = no_of_test + 1;
if (DATA !== load_data)
$write("[TEST] Read %1b, Write %1b, Addr %7h, expecting %8h, got %8h [FAILED]\n",
READ, WRITE, ADDR, load_data, DATA);
else
no_of_pass = no_of_pass + 1;
load_data = load_data + 1;
end
#10 READ=1'b0; WRITE=1'b0; // No op
#10 $write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/mem_dump_01.dat", mem_inst.sram_32x64m, 'h0000000, 'h000000f);
$writememh("./OUTPUT/mem_dump_02.dat", mem_inst.sram_32x64m, 'h0001000, 'h000100f);
$stop;
end
endmodule;

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// Name: mult_tb.v
// Module: MULT_U_TB, MULT_TB
//
// Notes: - Testbench for multiplier
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MULT_U_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
// outputs to observe
wire [`DATA_INDEX_LIMIT:0] HI, LO;
// result registers
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:4];
MULT32_U mult32_u_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
initial
begin
i=0;
A=10; B=20; // Y = 10 * 20 = 200
#1 result[i] = {HI,LO}; i=i+1;
#1 A=3; B=15; // Y = 3 * 15 = 45
#1 result[i] = {HI,LO}; i=i+1;
#1 A=16; B=7; // Y = 16 * 7 = 112
#1 result[i] = {HI,LO}; i=i+1;
#1 A=10; B=19; // Y = 10 * 19 = 190
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1
$writememh("./OUTPUT/mult32_u_tb.out", result);
$stop;
end
endmodule
module MULT_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
// outputs to observe
wire [`DATA_INDEX_LIMIT:0] HI, LO;
// result registers
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:7];
MULT32 mult32_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
initial
begin
i=0;
A=10; B=20; // Y = 10 * 20 = 200
#1 result[i] = {HI,LO}; i=i+1;
#1 A=-3; B=-15; // Y = 3 * 15 = 45
#1 result[i] = {HI,LO}; i=i+1;
#1 A=-16; B=7; // Y = 16 * 7 = -112
#1 result[i] = {HI,LO}; i=i+1;
#1 A=10; B=-19; // Y = 10 * 19 = -190
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h90000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h90000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h90000000; B=32'h90000000;
#1 result[i] = {HI,LO}; i=i+1;
#1
$writememh("./OUTPUT/mult32_tb.out", result);
$stop;
end
endmodule

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// Name: mux32_tb.v
// Module: MUX32_2x1_TB
// MUX32_16x1_TB
// MUX32_32x1_TB
//
// Notes: - Testbench for different multiplexer
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MUX32_32x1_TB;
reg [31:0] I [0:31];
reg [4:0] S;
wire [31:0] Y;
integer i;
reg [31:0] result [0:31];
MUX32_32x1 mux_inst_01(.Y(Y),
.I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]),
.I4(I[4]), .I5(I[5]), .I6(I[6]), .I7(I[7]),
.I8(I[8]), .I9(I[9]), .I10(I[10]), .I11(I[11]),
.I12(I[12]), .I13(I[13]), .I14(I[14]), .I15(I[15]),
.I16(I[16]), .I17(I[17]), .I18(I[18]), .I19(I[19]),
.I20(I[20]), .I21(I[21]), .I22(I[22]), .I23(I[23]),
.I24(I[24]), .I25(I[25]), .I26(I[26]), .I27(I[27]),
.I28(I[28]), .I29(I[29]), .I30(I[30]), .I31(I[31]),
.S(S));
initial
begin
for(i=0;i<32;i=i+1)
I[i]=i;
for(i=0;i<32;i=i+1)
begin
#1 S = i;
#1 result[i]=Y;
end
#1
$writememh("./OUTPUT/mux32_32x1_tb.out", result);
$stop;
end
endmodule
module MUX32_16x1_TB;
reg [31:0] I [0:15];
reg [3:0] S;
wire [31:0] Y;
integer i;
reg [31:0] result [0:15];
MUX32_16x1 mux_inst_01(.Y(Y),
.I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]),
.I4(I[4]), .I5(I[5]), .I6(I[6]), .I7(I[7]),
.I8(I[8]), .I9(I[9]), .I10(I[10]), .I11(I[11]),
.I12(I[12]), .I13(I[13]), .I14(I[14]), .I15(I[15]),
.S(S));
initial
begin
for(i=0;i<16;i=i+1)
I[i]=i;
for(i=0;i<16;i=i+1)
begin
#1 S = i;
#1 result[i]=Y;
end
#1
$writememh("./OUTPUT/mux32_16x1_tb.out", result);
$stop;
end
endmodule
module MUX32_2x1_TB;
reg [31:0] I0, I1;
reg S;
wire [31:0] Y;
reg [31:0] result [0:1];
MUX32_2x1 mux_inst_01(.Y(Y), .I0(I0), .I1(I1), .S(S));
initial
begin
I0 = 32'hA5A5A5A5; I1 = 32'h5A5A5A5A; S=1'b0;
#1 result[0] = Y;
#1 S=1'b1;
#1 result[1] = Y;
#1
$writememh("./OUTPUT/mux32_2x1_tb.out", result);
$stop;
end
endmodule

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// Name: rc_add_sub_32_tb.v
// Module: RC_ADD_SUB_32_TB
//
// Notes: - Testbench for RC adder/asubtractor
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module RC_ADD_SUB_32_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
reg SnA;
// outputs to observe
wire CO;
wire [`DATA_INDEX_LIMIT:0] Y;
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:4];
RC_ADD_SUB_32 rc_add_sub_inst(.Y(Y), .CO(CO), .A(A), .B(B), .SnA(SnA));
initial
begin
i=0;
A=10; B=20; SnA=1'b0; // Y = 10 + 20 = 30
#1 result[i] = Y; i=i+1;
#1 A=10; B=20; SnA=1'b1; // Y = 10 - 20 = -10
#1 result[i] = Y; i=i+1;
#1 A=15; B=12; SnA=1'b1; // Y = 15 - 12 = 3
#1 result[i] = Y; i=i+1;
#1 A=0; B=4; SnA=1'b0; // Y = 0 + 4 = 4
#1 result[i] = Y; i=i+1;
#1 A=32'h80001234; B=32'h80004321; SnA=1'b0;
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/rc_add_sub_32.out",result);
$stop;
end
endmodule

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// Name: proj_2_tb.v
// Module: RF_TB
//
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for MEMORY_64MB memory system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module RF_TB;
// Storage list
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_W;
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1;
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_R2;
// reset
reg READ, WRITE, RST;
// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;
// wire lists
wire CLK;
wire [`DATA_INDEX_LIMIT:0] DATA_R1;
wire [`DATA_INDEX_LIMIT:0] DATA_R2;
// result
integer ridx;
reg [`DATA_INDEX_LIMIT:0] result [0:63];
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// 64MB memory instance
REGISTER_FILE_32x32 ref_32x32_inst(.DATA_R1(DATA_R1), .DATA_R2(DATA_R2), .ADDR_R1(ADDR_R1),
.ADDR_R2(ADDR_R2), .DATA_W(DATA_REG), .ADDR_W(ADDR_W),
.READ(READ), .WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
ridx=0;
RST=1'b1;
READ=1'b0;
WRITE=1'b0;
DATA_REG = {`DATA_WIDTH{1'b0} };
ADDR_R1 = {`DATA_WIDTH{1'b0} };
ADDR_R2 = {`DATA_WIDTH{1'b0} };
no_of_test = 0;
no_of_pass = 0;
// Start the operation
#10 RST=1'b0;
#10 RST=1'b1;
// Write cycle
for(i=0;i<32; i = i + 1)
begin
#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
end
#5 READ=1'b0; WRITE=1'b0;
// test of write data
for(i=0;i<32; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
#5 no_of_test = no_of_test + 1;
if (DATA_R1 !== i)
$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
else
no_of_pass = no_of_pass + 1;
result[ridx] = DATA_R1; ridx=ridx+1;
result[ridx] = DATA_R1; ridx=ridx+1;
end
#5 READ=1'b0; WRITE=1'b0; // No op
#10 $write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/rf_tb.out",result);
$stop;
end
endmodule

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// Name: alu.v
// Module: ALU
// Input: OP1[32] - operand 1
// OP2[32] - operand 2
// OPRN[6] - operation code
// Output: OUT[32] - output result for the operation
//
// Notes: 32 bit combinatorial ALU
//
// Supports the following functions
// - Integer add (0x1), sub(0x2), mul(0x3)
// - Integer shift_rigth (0x4), shift_left (0x5)
// - Bitwise and (0x6), or (0x7), nor (0x8)
// - set less than (0x9)
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
module ALU(OUT, ZERO, OP1, OP2, OPRN);
// input list
input [`DATA_INDEX_LIMIT:0] OP1; // operand 1
input [`DATA_INDEX_LIMIT:0] OP2; // operand 2
input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
// output list
output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
output ZERO;
// TBD
endmodule

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// Name: barrel_shifter.v
// Module: SHIFT32_L , SHIFT32_R, SHIFT32
//
// Notes: 32-bit barrel shifter
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
// 32-bit shift amount shifter
module SHIFT32(Y,D,S, LnR);
// output list
output [31:0] Y;
// input list
input [31:0] D;
input [31:0] S;
input LnR;
// TBD
endmodule
// Shift with control L or R shift
module BARREL_SHIFTER32(Y,D,S, LnR);
// output list
output [31:0] Y;
// input list
input [31:0] D;
input [4:0] S;
input LnR;
// TBD
endmodule
// Right shifter
module SHIFT32_R(Y,D,S);
// output list
output [31:0] Y;
// input list
input [31:0] D;
input [4:0] S;
// TBD
endmodule
// Left shifter
module SHIFT32_L(Y,D,S);
// output list
output [31:0] Y;
// input list
input [31:0] D;
input [4:0] S;
// TBD
endmodule

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// Name: clk_gen.v
// Module: CLK_GENERATOR
//
// Output: CLK - output clock with period `SYS_CLK_FREQ
//
// Notes: Clock generator. The clock frequency is defined in the project definition file.
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module CLK_GENERATOR(CLK);
// output list;
output CLK;
// storage for clock value
reg CLK;
initial
begin
CLK = 1'b1;
end
// For ever perform the following task.
always
begin
#`SYS_CLK_HALF_PERIOD CLK <= ~CLK;
end
endmodule;

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// Name: control_unit.v
// Module: CONTROL_UNIT
// Output: CTRL : Control signal for data path
// READ : Memory read signal
// WRITE : Memory Write signal
//
// Input: ZERO : Zero status from ALU
// CLK : Clock signal
// RST : Reset Signal
//
// Notes: - Control unit synchronize operations of a processor
// Assign each bit of control signal to control one part of data path
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
// Output signals
output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
output READ, WRITE;
// input signals
input ZERO, CLK, RST;
input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
// TBD - take action on each +ve edge of clock
endmodule
//------------------------------------------------------------------------------------------
// Module: PROC_SM
// Output: STATE : State of the processor
//
// Input: CLK : Clock signal
// RST : Reset signal
//
// INOUT: MEM_DATA : Data to be read in from or write to the memory
//
// Notes: - Processor continuously cycle witnin fetch, decode, execute,
// memory, write back state. State values are in the prj_definition.v
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
module PROC_SM(STATE,CLK,RST);
// list of inputs
input CLK, RST;
// list of outputs
output [2:0] STATE;
// TBD - take action on each +ve edge of clock
endmodule

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// Name: da_vinci.v
// Module: DA_VINCI
//
// Outputs are for testbench observations only
//
// Output: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - 32 bit bareminimum computer system DA_VINCI_v1.0 implementing cs147sec05 instruction set
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module DA_VINCI (MEM_DATA_OUT, MEM_DATA_IN, ADDR, READ, WRITE, CLK, RST);
// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
output READ, WRITE;
// input list
input CLK, RST;
// Instance section
// Processor instanceIN
PROC_CS147_SEC05 processor_inst(.DATA_IN(MEM_DATA_OUT), .DATA_OUT(MEM_DATA_IN),
.ADDR(ADDR), .READ(READ),
.WRITE(WRITE), .CLK(CLK), .RST(RST));
// memory instance
defparam memory_inst.mem_init_file = mem_init_file;
MEMORY_WRAPPER memory_inst(.DATA_OUT(MEM_DATA_OUT), .DATA_IN(MEM_DATA_IN),
.READ(READ), .WRITE(WRITE),
.ADDR(ADDR), .CLK(CLK), .RST(RST));
endmodule;

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// Name: data_path.v
// Module: DATA_PATH
// Output: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - 32 bit processor implementing cs147sec05 instruction set
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST);
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output ZERO;
output [`DATA_INDEX_LIMIT:0] DATA_OUT, INSTRUCTION;
// input list
input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
input CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_IN;
// TBD
endmodule

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// Name: full_adder.v
// Module: FULL_ADDER
//
// Output: S : Sum
// CO : Carry Out
//
// Input: A : Bit 1
// B : Bit 2
// CI : Carry In
//
// Notes: 1-bit full adder implementaiton.
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module FULL_ADDER(S,CO,A,B, CI);
output S,CO;
input A,B, CI;
//TBD
endmodule;

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// Name: half_adder.v
// Module: HALF_ADDER
//
// Output: Y : Sum
// C : Carry
//
// Input: A : Bit 1
// B : Bit 2
//
// Notes: 1-bit half adder implementaiton.
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module HALF_ADDER(Y,C,A,B);
output Y,C;
input A,B;
// TBD
endmodule;

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// Name: logic.v
// Module:
// Input:
// Output:
//
// Notes: Common definitions
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
// 64-bit two's complement
module TWOSCOMP64(Y,A);
//output list
output [63:0] Y;
//input list
input [63:0] A;
// TBD
endmodule
// 32-bit two's complement
module TWOSCOMP32(Y,A);
//output list
output [31:0] Y;
//input list
input [31:0] A;
// TBD
endmodule
// 32-bit registere +ve edge, Reset on RESET=0
module REG32(Q, D, LOAD, CLK, RESET);
output [31:0] Q;
input CLK, LOAD;
input [31:0] D;
input RESET;
// TBD
endmodule
// 1 bit register +ve edge,
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module REG1(Q, Qbar, D, L, C, nP, nR);
input D, C, L;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
// 1 bit flipflop +ve edge,
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module D_FF(Q, Qbar, D, C, nP, nR);
input D, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
// 1 bit D latch
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module D_LATCH(Q, Qbar, D, C, nP, nR);
input D, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
// 1 bit SR latch
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module SR_LATCH(Q,Qbar, S, R, C, nP, nR);
input S, R, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
// 5x32 Line decoder
module DECODER_5x32(D,I);
// output
output [31:0] D;
// input
input [4:0] I;
// TBD
endmodule
// 4x16 Line decoder
module DECODER_4x16(D,I);
// output
output [15:0] D;
// input
input [3:0] I;
// TBD
endmodule
// 3x8 Line decoder
module DECODER_3x8(D,I);
// output
output [7:0] D;
// input
input [2:0] I;
//TBD
endmodule
// 2x4 Line decoder
module DECODER_2x4(D,I);
// output
output [3:0] D;
// input
input [1:0] I;
// TBD
endmodule

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// Name: logic_32_bit.v
// Module:
// Input:
// Output:
//
// Notes: Common definitions
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
// 32-bit NOR
module NOR32_2x1(Y,A,B);
//output
output [31:0] Y;
//input
input [31:0] A;
input [31:0] B;
// TBD
endmodule
// 32-bit AND
module AND32_2x1(Y,A,B);
//output
output [31:0] Y;
//input
input [31:0] A;
input [31:0] B;
// TBD
endmodule
// 32-bit inverter
module INV32_1x1(Y,A);
//output
output [31:0] Y;
//input
input [31:0] A;
// TBD
endmodule
// 32-bit OR
module OR32_2x1(Y,A,B);
//output
output [31:0] Y;
//input
input [31:0] A;
input [31:0] B;
// TBD
endmodule

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// Name: memory.v
// Module: MEMORY_64MB
// Input: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
// CLK : Clock signal
// RST : Reset signal
// Output: DATA : Data read out in the read operation
//
// Notes: - 32 bit word accessible 64MB memory.
// - Reset is done at -ve edge of the RST signal
// - Rest of the operation is done at the +ve edge of the CLK signal
// - Read operation is done if READ=1 and WRITE=0
// - Write operation is done if WRITE=1 and READ=0
// - X is the value at DATA if both READ and WRITE are 0 or 1
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
module MEMORY_WRAPPER(DATA_OUT, DATA_IN, READ, WRITE, ADDR, CLK, RST);
// parameter file
// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";
// output list
output [`DATA_INDEX_LIMIT:0] DATA_OUT;
//input list
input [`DATA_INDEX_LIMIT:0] DATA_IN;
input READ, WRITE, CLK, RST;
input [`ADDRESS_INDEX_LIMIT:0] ADDR;
reg [`DATA_INDEX_LIMIT:0] DATA_OUT;
wire [`DATA_INDEX_LIMIT:0] DATA;
assign DATA = ((READ===1'b0)&&(WRITE===1'b1))?DATA_IN:{`DATA_WIDTH{1'bz} };
defparam memory_inst.mem_init_file = mem_init_file;
MEMORY_64MB memory_inst(.DATA(DATA), .READ(READ), .WRITE(WRITE),
.ADDR(ADDR), .CLK(CLK), .RST(RST));
initial
begin
DATA_OUT = 32'h00000000;
end
always @(negedge RST)
begin
if (RST === 1'b0)
DATA_OUT = 32'h00000000;
end
always @(DATA)
begin
if ((READ===1'b1)&&(WRITE===1'b0))
DATA_OUT=DATA;
end
endmodule
module MEMORY_64MB(DATA, READ, WRITE, ADDR, CLK, RST);
// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";
// input ports
input READ, WRITE, CLK, RST;
input [`ADDRESS_INDEX_LIMIT:0] ADDR;
// inout ports
inout [`DATA_INDEX_LIMIT:0] DATA;
// memory bank
reg [`DATA_INDEX_LIMIT:0] sram_32x64m [0:`MEM_INDEX_LIMIT]; // memory storage
integer i; // index for reset operation
reg [`DATA_INDEX_LIMIT:0] data_ret; // return data register
assign DATA = ((READ===1'b1)&&(WRITE===1'b0))?data_ret:{`DATA_WIDTH{1'bz} };
always @ (negedge RST or posedge CLK)
begin
if (RST === 1'b0)
begin
for(i=0;i<=`MEM_INDEX_LIMIT; i = i +1)
sram_32x64m[i] = { `DATA_WIDTH{1'b0} };
$readmemh(mem_init_file, sram_32x64m);
end
else
begin
if ((READ===1'b1)&&(WRITE===1'b0)) // read operation
data_ret = sram_32x64m[ADDR];
else if ((READ===1'b0)&&(WRITE===1'b1)) // write operation
sram_32x64m[ADDR] = DATA;
end
end
endmodule

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// Name: mult.v
// Module: MULT32 , MULT32_U
//
// Output: HI: 32 higher bits
// LO: 32 lower bits
//
//
// Input: A : 32-bit input
// B : 32-bit input
//
// Notes: 32-bit multiplication
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module MULT32(HI, LO, A, B);
// output list
output [31:0] HI;
output [31:0] LO;
// input list
input [31:0] A;
input [31:0] B;
// TBD
endmodule
module MULT32_U(HI, LO, A, B);
// output list
output [31:0] HI;
output [31:0] LO;
// input list
input [31:0] A;
input [31:0] B;
// TBD
endmodule

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// Name: mux.v
// Module:
// Input:
// Output:
//
// Notes: Common definitions
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
// 32-bit mux
module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
I8, I9, I10, I11, I12, I13, I14, I15,
I16, I17, I18, I19, I20, I21, I22, I23,
I24, I25, I26, I27, I28, I29, I30, I31, S);
// output list
output [31:0] Y;
//input list
input [31:0] I0, I1, I2, I3, I4, I5, I6, I7;
input [31:0] I8, I9, I10, I11, I12, I13, I14, I15;
input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
input [4:0] S;
// TBD
endmodule
// 32-bit 16x1 mux
module MUX32_16x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
I8, I9, I10, I11, I12, I13, I14, I15, S);
// output list
output [31:0] Y;
//input list
input [31:0] I0;
input [31:0] I1;
input [31:0] I2;
input [31:0] I3;
input [31:0] I4;
input [31:0] I5;
input [31:0] I6;
input [31:0] I7;
input [31:0] I8;
input [31:0] I9;
input [31:0] I10;
input [31:0] I11;
input [31:0] I12;
input [31:0] I13;
input [31:0] I14;
input [31:0] I15;
input [3:0] S;
// TBD
endmodule
// 32-bit 8x1 mux
module MUX32_8x1(Y, I0, I1, I2, I3, I4, I5, I6, I7, S);
// output list
output [31:0] Y;
//input list
input [31:0] I0;
input [31:0] I1;
input [31:0] I2;
input [31:0] I3;
input [31:0] I4;
input [31:0] I5;
input [31:0] I6;
input [31:0] I7;
input [2:0] S;
// TBD
endmodule
// 32-bit 4x1 mux
module MUX32_4x1(Y, I0, I1, I2, I3, S);
// output list
output [31:0] Y;
//input list
input [31:0] I0;
input [31:0] I1;
input [31:0] I2;
input [31:0] I3;
input [1:0] S;
// TBD
endmodule
// 32-bit mux
module MUX32_2x1(Y, I0, I1, S);
// output list
output [31:0] Y;
//input list
input [31:0] I0;
input [31:0] I1;
input S;
// TBD
endmodule
// 1-bit mux
module MUX1_2x1(Y,I0, I1, S);
//output list
output Y;
//input list
input I0, I1, S;
// TBD
endmodule

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// Name: prj_definition.v
// Module:
// Input:
// Output:
//
// Notes: Common definitions
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`timescale 1ns/10ps
`define SYS_CLK_PERIOD 10
`define SYS_CLK_HALF_PERIOD (`SYS_CLK_PERIOD/2)
`define DATA_WIDTH 32
`define DATA_INDEX_LIMIT (`DATA_WIDTH -1)
`define ALU_OPRN_WIDTH 6
`define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1)
`define ADDRESS_WIDTH 26
`define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1)
`define MEM_SIZE (2 ** `ADDRESS_WIDTH)
`define MEM_INDEX_LIMIT (`MEM_SIZE - 1)
`define NUM_OF_REG 32
`define REG_INDEX_LIMIT (`NUM_OF_REG -1)
`define REG_ADDR_INDEX_LIMIT 4
`define CTRL_WIDTH 32
`define CTRL_WIDTH_INDEX_LIMIT (`CTRL_WIDTH - 1)
`define DOUBLE_DATA_WIDTH 64
`define DOUBLE_DATA_INDEX_LIMIT (`DOUBLE_DATA_WIDTH - 1)
// definition for processor state
`define PROC_FETCH 3'h0
`define PROC_DECODE 3'h1
`define PROC_EXE 3'h2
`define PROC_MEM 3'h3
`define PROC_WB 3'h4
// define ISA parameters
`define INST_START_ADDR 32'h00001000
`define INIT_STACK_POINTER 32'h03ffffff

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// Name: processor.v
// Module: PROC_CS147_SEC05
// Output: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - 32 bit processor implementing cs147sec05 instruction set
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
// 1.1 Oct 19, 2014 Kaushik Patra kpatra@sjsu.edu Fixed the RF connection
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
module PROC_CS147_SEC05(DATA_OUT, ADDR, DATA_IN, READ, WRITE, CLK, RST);
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output [`DATA_INDEX_LIMIT:0] DATA_OUT;
output READ, WRITE;
// input list
input CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_IN;
// net section
wire zero;
wire [`CTRL_WIDTH_INDEX_LIMIT:0] ctrl;
wire [`DATA_INDEX_LIMIT:0] INSTRUCTION;
// instantiation section
// Control unit
CONTROL_UNIT cu_inst (.CTRL(ctrl), .READ(READ), .WRITE(WRITE),
.ZERO(zero), .INSTRUCTION(INSTRUCTION),
.CLK(CLK), .RST(RST));
// data path
DATA_PATH data_path_inst (.DATA_OUT(DATA_OUT), .INSTRUCTION(INSTRUCTION), .DATA_IN(DATA_IN), .ADDR(ADDR), .ZERO(zero),
.CTRL(ctrl), .CLK(CLK), .RST(RST));
endmodule;

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// Name: rc_add_sub_32.v
// Module: RC_ADD_SUB_32
//
// Output: Y : Output 32-bit
// CO : Carry Out
//
//
// Input: A : 32-bit input
// B : 32-bit input
// SnA : if SnA=0 it is add, subtraction otherwise
//
// Notes: 32-bit adder / subtractor implementaiton.
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "prj_definition.v"
module RC_ADD_SUB_64(Y, CO, A, B, SnA);
// output list
output [63:0] Y;
output CO;
// input list
input [63:0] A;
input [63:0] B;
input SnA;
// TBD
endmodule
module RC_ADD_SUB_32(Y, CO, A, B, SnA);
// output list
output [`DATA_INDEX_LIMIT:0] Y;
output CO;
// input list
input [`DATA_INDEX_LIMIT:0] A;
input [`DATA_INDEX_LIMIT:0] B;
input SnA;
// TBD
endmodule

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// Name: register_file.v
// Module: REGISTER_FILE_32x32
// Input: DATA_W : Data to be written at address ADDR_W
// ADDR_W : Address of the memory location to be written
// ADDR_R1 : Address of the memory location to be read for DATA_R1
// ADDR_R2 : Address of the memory location to be read for DATA_R2
// READ : Read signal
// WRITE : Write signal
// CLK : Clock signal
// RST : Reset signal
// Output: DATA_R1 : Data at ADDR_R1 address
// DATA_R2 : Data at ADDR_R1 address
//
// Notes: - 32 bit word accessible dual read register file having 32 regsisters.
// - Reset is done at -ve edge of the RST signal
// - Rest of the operation is done at the +ve edge of the CLK signal
// - Read operation is done if READ=1 and WRITE=0
// - Write operation is done if WRITE=1 and READ=0
// - X is the value at DATA_R* if both READ and WRITE are 0 or 1
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
// This is going to be +ve edge clock triggered register file.
// Reset on RST=0
module REGISTER_FILE_32x32(DATA_R1, DATA_R2, ADDR_R1, ADDR_R2,
DATA_W, ADDR_W, READ, WRITE, CLK, RST);
// input list
input READ, WRITE, CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_W;
input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
// output list
output [`DATA_INDEX_LIMIT:0] DATA_R1;
output [`DATA_INDEX_LIMIT:0] DATA_R2;
// TBD
endmodule