CaZzzer/cs147dv
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

control unit: fix stack pointer inc/dec, passing SP15, FL15, RevFib

Browse Source
This commit is contained in:
Yuri Tatishchev 2024-11-18 23:00:06 -08:00
parent 507fa2e863
commit 0198e8be41
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
4 changed files with 38 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
OUTPUT/CS147_FL15_HW01_02_mem_dump.dat
View File

@ -1,13 +1,13 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000020
00000020
00000010
00000010
00000009
00000008
00000008
00000005
00000004
00000002

8
OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat
View File

@ -2,8 +2,8 @@
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00000020
00000008
00000008
00000002
00000002

30
OUTPUT/RevFib_mem_dump.dat
View File

@ -1,19 +1,19 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
ffffffc9
00000022
ffffffeb
0000000d
fffffff8
00000005
fffffffd
00000002
ffffffff
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000059
00000001
00000001
00000002
00000003
00000005

13
control_unit.v
View File

@ -239,6 +239,8 @@ always @ (state) begin
print_instruction(INSTRUCTION);
// loaded in previous state, set to 0
C[`ir_load] = 1'b0;
// load now
C[`sp_load] = opcode == `OP_POP; // sp is decremented before pop
// selections
// r1_sel_1: rs by default (0), push - r1 (1)
C[`r1_sel_1] = opcode == `OP_PUSH;
@ -294,13 +296,14 @@ always @ (state) begin
end
// op1_sel_1: r1 by default (0), push or pop - sp (1)
C[`op1_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP;
// op2_sel_1: const 1 (for inc/dec) (0), shamnt for sll/srl (1)
// op2_sel_1: const 1 (for inc/dec) (0), shamt for sll/srl (1)
C[`op2_sel_1] = opcode == `OP_RTYPE && (funct == `FN_SLL || funct == `FN_SRL);
// op2_sel_2: imm_zx for logical and/or (0), imm_sx otherise (1)
// ('nor' not availble in I-type)
C[`op2_sel_2] = ~(opcode == `OP_ANDI || opcode == `OP_ORI);
// op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift (1)
C[`op2_sel_3] = opcode == `OP_RTYPE;
// op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift or inc/dec (1)
// inc/dec is push or pop
C[`op2_sel_3] = opcode == `OP_RTYPE || opcode == `OP_PUSH || opcode == `OP_POP;
// op2_sel_4: op2_sel_3 for I-type (except beq, bne) or R-type shift or inc/dec (0), else r2 (1)
// i.e. r2 if R-type (except sll/srl), or bne/beq
C[`op2_sel_4] = opcode == `OP_RTYPE && ~(funct == `FN_SLL || funct == `FN_SRL)
@ -322,12 +325,16 @@ always @ (state) begin
C[`md_sel_1] = opcode == `OP_PUSH;
end
`PROC_MEM: begin
// loaded in previous state, set to 0
C[`sp_load] = 1'b0;
// push or sw - write to memory
write = opcode == `OP_PUSH || opcode == `OP_SW;
// pop or lw - read from memory
read = opcode == `OP_POP || opcode == `OP_LW;
end
`PROC_WB: begin
// load now
C[`sp_load] = opcode == `OP_PUSH; // sp is incremented after push
// loaded in previous state, set to 0
read = 1'b0;
write = 1'b0;