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control unit: fix jal, add comprehensive instruction test

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This commit is contained in:
Yuri Tatishchev 2024-11-20 00:52:11 -08:00
parent 0198e8be41
commit ceba9d6fd5
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
5 changed files with 103 additions and 6 deletions
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21
OUTPUT/all_test_mem_dump_01.dat Normal file
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@ -0,0 +1,21 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00001337
000039a5
00002024
0000335b
fffff313
00000ced
026993bc
00000024
00003337
ffffccc8
00000001
00000000
00013370
00000133
000039a5
00000005
00000005
fffff313

9
OUTPUT/all_test_mem_dump_02.dat Normal file
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@ -0,0 +1,9 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00001337

20
TESTBENCH/da_vinci_tb.v
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@ -30,7 +30,8 @@ wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
// reset
reg RST;
integer t1=1, t2=1, t3=1, t4=1, t5=1;
//integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
@ -129,6 +130,23 @@ begin
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048005);
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
/* END : test 5*/
end
if (t6 === 1)
begin
/* START : test 6*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating all_test.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/all_test.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating all_test.dat\n", "");
$write("\n");
$writememh("./OUTPUT/all_test_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048011);
$writememh("./OUTPUT/all_test_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
/* END : test 6*/
end
$stop;

49
TESTPROGRAM/all_test.dat Normal file
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@ -0,0 +1,49 @@
@0001000
20001337 // addi r0, r0, 0x1337
6c000000 // push
3c1e0004 // lui r30, 0x0004
37de8000 // ori r30, r30 0x00008000
afc00000 // sw r0, r30, 0x0
0c001014 // jal 0x00001014
70000000 // pop
20212024 // addi r1, r1, 0x2024
00011020 // add r2, r0, r1
00011822 // sub r3, r0, r1
00202022 // sub r4, r1, r0
0001282c // mul r5, r0, r1
00013024 // and r6, r0, r1
00013825 // or r7, r0, r1
00014027 // nor r8, r0, r1
0001482a // slt r9, r0, r1
0020502a // slt r10, r1, r0
00005901 // sll r11, r0, 4
00006102 // srl r12, r0, 4
08001017 // jmp 0x00001017
74000003 // muli r0, r0, 3
afc00001 // sw r0, r30, 0x1
03e00008 // jr r31
8fcd0001 // lw r13, r30, 0x1
29ae1338 // slti r14, r13, 0x1338
302f0000 // andi r15, r1, 0x0
21ef0005 // addi r15, r15, 0x5
11ee0002 // beq r14, r15, 0x2
21ce0001 // addi r14, r14, 0x1
0800101b // jmp 0x0000101b
afc10002 // sw r1, r30, 0x2
afc20003 // sw r2, r30, 0x3
afc30004 // sw r3, r30, 0x4
afc40005 // sw r4, r30, 0x5
afc50006 // sw r5, r30, 0x6
afc60007 // sw r6, r30, 0x7
afc70008 // sw r7, r30, 0x8
afc80009 // sw r8, r30, 0x9
afc9000a // sw r9, r30, 0x0a
afca000b // sw r10, r30, 0x0b
afcb000c // sw r11, r30, 0x0c
afcc000d // sw r12, r30, 0x0d
afcd000e // sw r13, r30, 0x0e
afce000f // sw r14, r30, 0x0f
afcf0010 // sw r15, r30, 0x10
2210fbb1 // addi r16, r16, 0xfbb1
1470fffe // bne r16, r3, 0xfffe
afd00011 // sw r16, r30, 0x11

10
control_unit.v
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@ -246,13 +246,13 @@ always @ (state) begin
C[`r1_sel_1] = opcode == `OP_PUSH;
// wa_sel_1: R-type - write to rd (0), I-type - write to rt (1)
C[`wa_sel_1] = opcode != `OP_RTYPE;
// wa_sel_2: jal - write to r31 (0), pop - write to r0 (1)
C[`wa_sel_2] = opcode == `OP_POP;
// wa_sel_2: pop - write to r0 (0), jal - write to r31 (1)
C[`wa_sel_2] = opcode == `OP_JAL;
// wa_sel_3: push or pop - wa_sel_2, else wa_sel_1
// wa_sel_3: wa_sel_2 if push or pop (0), else wa_sel_1 (1)
C[`wa_sel_3] = ~(opcode == `OP_PUSH || opcode == `OP_POP);
// wa_sel_3: wa_sel_2 if push or pop or jal (0), else wa_sel_1 (1)
C[`wa_sel_3] = ~(opcode == `OP_PUSH || opcode == `OP_POP || opcode == `OP_JAL);
// pc_sel_1: jr - jump to address in rs (0), else pc_inc (1)
C[`pc_sel_1] = ~(opcode == `OP_JMP && funct == `FN_JR);
C[`pc_sel_1] = ~(opcode == `OP_RTYPE && funct == `FN_JR);
// pc_sel_2: pc_sel_1 by default (0), beq, bne - branch if equal or not equal (1)
// TODO: this should only be selected if the condition is met
// pc_sel_2 = opcode == `OP_BEQ || opcode == `OP_BNE;