lab-07: gate level model for 32-bit register

Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32

logic.v

@@ -43,7 +43,12 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-// TBD
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1) begin : reg_gen
+        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
+    end
+endgenerate
 
 endmodule
 
@@ -122,7 +127,19 @@ output [31:0] D;
 // input
 input [4:0] I;
 
-// TBD
+wire [15:0] half;
+wire I_not;
+not I_inv(I_not, I[4]);
+
+DECODER_4x16 d(half, I[3:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 16; i = i + 1) begin : d5_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 16], I[4], half[i]);
+    end
+endgenerate
 
 endmodule
 
@@ -133,7 +150,19 @@ output [15:0] D;
 // input
 input [3:0] I;
 
-// TBD
+wire [7:0] half;
+wire I_not;
+not I_inv(I_not, I[3]);
+
+DECODER_3x8 d(half, I[2:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 8; i = i + 1) begin : d4_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 8], I[3], half[i]);
+    end
+endgenerate
 
 
 endmodule
@@ -145,8 +174,19 @@ output [7:0] D;
 // input
 input [2:0] I;
 
-//TBD
+wire [3:0] half;
+wire I_not;
+not I_inv(I_not, I[2]);
 
+DECODER_2x4 d(half, I[1:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 4; i = i + 1) begin : d3_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 4], I[2], half[i]);
+    end
+endgenerate
 
 endmodule
 

mux.v

@@ -27,7 +27,16 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
 input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
 input [4:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
+                       I8, I9, I10, I11, I12, I13, I14, I15,
+                       S[3:0]
+);
+MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
+                       I24, I25, I26, I27, I28, I29, I30, I31,
+                       S[3:0]
+);
+MUX32_2x1 out(Y, x0, x1, S[4]);
 
 endmodule
 

register_file.v

@@ -41,6 +41,31 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// TBD
+// module REG32(Q, D, LOAD, CLK, RESET);
+// module DECODER_5x32(D,I);
+
+// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
+                     // I8, I9, I10, I11, I12, I13, I14, I15,
+                     // I16, I17, I18, I19, I20, I21, I22, I23,
+                     // I24, I25, I26, I27, I28, I29, I30, I31, S);
+
+wire [31:0] Q [31:0];
+wire [31:0] write;
+DECODER_5x32 d_write(write, ADDR_W);
+
+REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
+
+MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R1
+);
+MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R2
+);
 
 endmodule