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lab-02: fix behavioral xor statement in RC_ADD_SUB modules

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This commit is contained in:
Yuri Tatishchev 2024-10-03 20:25:36 -07:00
parent 48bdad0e8b
commit f5b19ae9fc
Signed by: CaZzzer
GPG Key ID: 28BE602058C08557
1 changed files with 6 additions and 2 deletions
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8
rc_add_sub_32.v
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@ -37,7 +37,9 @@ genvar i;
generate
for (i = 0; i < 64; i = i + 1)
begin : add64_gen_loop
FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
wire B_xor;
xor (B_xor, B[i], SnA);
FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
end
endgenerate
@ -62,7 +64,9 @@ genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin : add32_gen_loop
FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
wire B_xor;
xor (B_xor, B[i], SnA);
FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
end
endgenerate