(WIP) lab-08: Register File
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@ -41,6 +41,31 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
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output [`DATA_INDEX_LIMIT:0] DATA_R1;
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output [`DATA_INDEX_LIMIT:0] DATA_R2;
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// TBD
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// module REG32(Q, D, LOAD, CLK, RESET);
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// module DECODER_5x32(D,I);
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// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
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// I8, I9, I10, I11, I12, I13, I14, I15,
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// I16, I17, I18, I19, I20, I21, I22, I23,
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// I24, I25, I26, I27, I28, I29, I30, I31, S);
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wire [31:0] Q [31:0];
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wire [31:0] write;
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DECODER_5x32 d_write(write, ADDR_W);
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REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
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MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
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Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
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Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
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Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
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ADDR_R1
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);
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MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
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Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
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Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
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Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
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ADDR_R2
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);
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endmodule
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