control unit: passing SP15 and SP17
This commit is contained in:
parent
b651f04748
commit
507fa2e863
GPG Key ID:
E0EBF441EA424369
@ -10,4 +10,4 @@
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00000000
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00000000
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00000000
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00000000
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00000020
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@ -6,4 +6,4 @@
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00000004
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00000010
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00000010
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00000040
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00000000
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@ -6,4 +6,4 @@
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00000000
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00000000
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00000000
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00000200
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00000020
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@ -1,14 +1,14 @@
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// memory data file (do not edit the following line - required for mem load use)
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// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
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// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
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00090001
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00090003
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00090005
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00090007
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00090009
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0009000b
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0009000d
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0009000f
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00090011
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00090013
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00090015
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00000015
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00000017
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00000019
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0000001b
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0000001d
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0000001f
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00000021
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00000023
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00000025
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00000025
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00000000
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197
control_unit.v
197
control_unit.v
@ -107,56 +107,56 @@ input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
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task print_instruction;
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input [`DATA_INDEX_LIMIT:0] inst;
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reg [5:0] opcode2;
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reg [4:0] rs2;
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reg [4:0] rt2;
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reg [4:0] rd2;
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reg [4:0] shamt2;
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reg [5:0] funct2;
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reg [15:0] immediate2;
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reg [25:0] address2;
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reg [5:0] opcode;
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reg [4:0] rs;
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reg [4:0] rt;
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reg [4:0] rd;
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reg [4:0] shamt;
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reg [5:0] funct;
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reg [15:0] imm;
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reg [25:0] addr;
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begin
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// parse the instruction
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// R-type
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{opcode2, rs2, rt2, rd2, shamt2, funct2} = inst;
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{opcode, rs, rt, rd, shamt, funct} = inst;
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// I-type
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{opcode2, rs2, rt2, immediate2 } = inst;
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{opcode, rs, rt, imm} = inst;
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// J-type
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{opcode2, address2} = inst;
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{opcode, addr} = inst;
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$write("@ %6dns -> [0X%08h] ", $time, inst);
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case(opcode2)
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case(opcode)
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// R-Type
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6'h00 : begin
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case(funct2)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
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6'h08: $write("jr r[%02d];", rs2);
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case(funct)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd, rs, shamt);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd, rs, shamt);
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6'h08: $write("jr r[%02d];", rs);
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default: $write("");
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endcase
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end
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// I-type
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt2, immediate2);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt, imm);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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// J-Type
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6'h02 : $write("jmp 0X%07h;", address2);
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6'h03 : $write("jal 0X%07h;", address2);
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6'h02 : $write("jmp 0X%07h;", addr);
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6'h03 : $write("jal 0X%07h;", addr);
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6'h1b : $write("push;");
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6'h1c : $write("pop;");
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default: $write("");
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@ -228,6 +228,7 @@ always @ (state) begin
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// decode - parse instruction and read values from register file
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`PROC_DECODE: begin
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// loaded in previous state, set to 0
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C[`ma_sel_2] = 1'b0;
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read = 1'b0;
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// load now
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C[`ir_load] = 1'b1;
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@ -239,21 +240,22 @@ always @ (state) begin
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// loaded in previous state, set to 0
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C[`ir_load] = 1'b0;
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// selections
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// r1_sel_1: push - store value of r0 at stack pointer
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C[`r1_sel_1] = opcode != 6'h1b ? 1'b0 : 1'b1;
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// wa_sel_1: R-type - write to rd, I-type - write to rt
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C[`wa_sel_1] = opcode == 6'h00 ? 1'b0 : 1'b1;
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// wa_sel_2: jal - write to r31, pop - write to r0
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C[`wa_sel_2] = opcode == 6'h03 ? 1'b1 : 1'b0;
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// r1_sel_1: rs by default (0), push - r1 (1)
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C[`r1_sel_1] = opcode == `OP_PUSH;
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// wa_sel_1: R-type - write to rd (0), I-type - write to rt (1)
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C[`wa_sel_1] = opcode != `OP_RTYPE;
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// wa_sel_2: jal - write to r31 (0), pop - write to r0 (1)
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C[`wa_sel_2] = opcode == `OP_POP;
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// wa_sel_3: push or pop - wa_sel_2, else wa_sel_1
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C[`wa_sel_3] = opcode == 6'h03 || opcode == 6'h1c ? 1'b0 : 1'b1;
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// jr - jump to address in register
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C[`pc_sel_1] = opcode == 6'h00 && funct == 6'h08 ? 1'b0 : 1'b1;
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// beq, bne - branch if equal or not equal
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// wa_sel_3: wa_sel_2 if push or pop (0), else wa_sel_1 (1)
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C[`wa_sel_3] = ~(opcode == `OP_PUSH || opcode == `OP_POP);
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// pc_sel_1: jr - jump to address in rs (0), else pc_inc (1)
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C[`pc_sel_1] = ~(opcode == `OP_JMP && funct == `FN_JR);
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// pc_sel_2: pc_sel_1 by default (0), beq, bne - branch if equal or not equal (1)
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// TODO: this should only be selected if the condition is met
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// pc_sel_2 = opcode == 6'h04 || opcode == 6'h05 ? 1'b1 : 1'b0;
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// jmp, jal - jump to address
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C[`pc_sel_3] = opcode == `OP_JMP || opcode == `OP_JAL ? 1'b0 : 1'b1;
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// pc_sel_2 = opcode == `OP_BEQ || opcode == `OP_BNE;
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// pc_sel_3: jmp or jal - jump to address (0), else pc_sel_2 (1)
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C[`pc_sel_3] = ~(opcode == `OP_JMP || opcode == `OP_JAL);
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// alu_oprn - operation to be performed by ALU
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// R-type
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@ -278,62 +280,52 @@ always @ (state) begin
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`OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi
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`OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli
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`OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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// J-type
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`OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// op1_sel_1 - select r1 or sp based on opcode
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// push or pop - sp, else r1
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C[`op1_sel_1] = opcode == 6'h1b || opcode == 6'h1c ? 1'b1 : 1'b0;
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// op2_sel_1 - select 1 or shamt based on alu_oprn
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// sll or srl - shamt, else 1 (for increments/decrements)
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C[`op2_sel_1] = C[`alu_oprn] == 6'h04 || C[`alu_oprn] == 6'h05 ? 1'b1 : 1'b0;
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// op2_sel_2 - select imm_zx or imm_sx based on alu_oprn
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// logical (and, or) - imm_zx, else imm_sx; ('nor' not availble in I-type)
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C[`op2_sel_2] = C[`alu_oprn] == 6'h06 || C[`alu_oprn] == 6'h07 ? 1'b0 : 1'b1;
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// op2_sel_3 - select op2_sel_2 or op2_sel_1 based on alu_oprn
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// R-type - op2_sel_1, I-type - op2_sel_2
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C[`op2_sel_3] = opcode == 6'h00 ? 1'b1 : 1'b0;
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// op2_sel_4 - select op2_sel_3 or r2
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// I-type or shift or inc/dec - op2_sel_3, else r2
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// i.e. r2 only if R-type and not shift
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C[`op2_sel_4] = opcode != 6'h00 || C[`alu_oprn] == 6'h04 || C[`alu_oprn] == 6'h05 ? 1'b0 : 1'b1;
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// op1_sel_1: r1 by default (0), push or pop - sp (1)
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C[`op1_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP;
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// op2_sel_1: const 1 (for inc/dec) (0), shamnt for sll/srl (1)
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C[`op2_sel_1] = opcode == `OP_RTYPE && (funct == `FN_SLL || funct == `FN_SRL);
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// op2_sel_2: imm_zx for logical and/or (0), imm_sx otherise (1)
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// ('nor' not availble in I-type)
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C[`op2_sel_2] = ~(opcode == `OP_ANDI || opcode == `OP_ORI);
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// op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift (1)
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C[`op2_sel_3] = opcode == `OP_RTYPE;
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// op2_sel_4: op2_sel_3 for I-type (except beq, bne) or R-type shift or inc/dec (0), else r2 (1)
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// i.e. r2 if R-type (except sll/srl), or bne/beq
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C[`op2_sel_4] = opcode == `OP_RTYPE && ~(funct == `FN_SLL || funct == `FN_SRL)
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|| opcode == `OP_BEQ || opcode == `OP_BNE;
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// wd_sel_1 - alu_out or DATA_IN
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C[`wd_sel_1] = 1'b0;
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// wd_sel_2 - wd_sel_1 or imm_zx_lsb
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// lui - imm_zx_lsb, else wd_sel_1
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C[`wd_sel_2] = opcode == 6'h0f ? 1'b1 : 1'b0;
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// wd_sel_3 - pc_inc or wd_sel_2
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// jal - pc_inc, else wd_sel_2
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C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1;
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// ma_sel_1 - alu_out for lw or sw, sp for push or pop
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C[`ma_sel_1] = opcode == `OP_LW || opcode == `OP_SW ? 1'b0 : 1'b1;
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// ma_sel_2 - 1 for pc, 0 for everything else
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C[`ma_sel_2] = opcode == `OP_LW || opcode == `OP_SW || opcode == `OP_PUSH || opcode == `OP_POP ? 1'b0 : 1'b1;
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// md_sel_1 - r1 for push, r2 for sw
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C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0;
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// wd_sel_1: alu_out or DATA_IN
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// wd_sel_1: alu_out by default (0), DATA_IN for lw or pop (1)
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C[`wd_sel_1] = opcode == `OP_LW || opcode == `OP_POP;
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// wd_sel_2: wd_sel_1 by default (0), imm_zx_lsb for lui (1)
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C[`wd_sel_2] = opcode == `OP_LUI;
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// wd_sel_3: pc_inc for jal (0), else wd_sel_2 (1)
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C[`wd_sel_3] = ~(opcode == `OP_JAL);
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// ma_sel_1: alu_out for lw or sw, sp for push or pop
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// ma_sel_1: alu_out for lw or sw (0), sp for push or pop (1)
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C[`ma_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP;
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// ma_sel_2: 0 for every memory access instruction (lw, sw, push, pop), 1 for fetch
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C[`ma_sel_2] = 1'b0;
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// md_sel_1: r2 for sw (0), r1 for push (1)
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C[`md_sel_1] = opcode == `OP_PUSH;
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end
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`PROC_MEM: begin
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// load now
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// push or sw - write to memory
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if (opcode == `OP_PUSH || opcode == `OP_SW) begin
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read = 1'b0;
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write = 1'b1;
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end
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else begin
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// read = 1'b1;
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// write = 1'b0;
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end
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write = opcode == `OP_PUSH || opcode == `OP_SW;
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// pop or lw - read from memory
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read = opcode == `OP_POP || opcode == `OP_LW;
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end
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`PROC_WB: begin
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// loaded in previous state, set to 0
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@ -343,15 +335,14 @@ always @ (state) begin
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C[`pc_load] = 1'b1;
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// write to register file if
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// R-type (except jr) or I-type (except beq, bne, sw) or pop or jal
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C[`reg_w] = (opcode == 6'h00 && funct != 6'h08) // R-type (except jr)
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|| (opcode == 6'h08 || opcode == 6'h1d || opcode == 6'h0c || opcode == 6'h0d
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|| opcode == 6'h0f || opcode == 6'h0a || opcode == 6'h23) // I-type (except beq, bne, sw)
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|| (opcode == 6'h1c || opcode == 6'h03) // pop or jal
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? 1'b1 : 1'b0;
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C[`reg_w] = (opcode == `OP_RTYPE && funct != `FN_JR) // R-type (except jr)
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|| (opcode == `OP_ADDI || opcode == `OP_MULI || opcode == `OP_ANDI || opcode == `OP_ORI
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|| opcode == `OP_LUI || opcode == `OP_SLTI || opcode == `OP_LW) // I-type (except beq, bne, sw)
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|| (opcode == `OP_POP || opcode == `OP_JAL) // pop or jal
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;
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// selections
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// pc_sel_2 - branch if equal or not equal
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C[`pc_sel_2] = (opcode == 6'h04 && ZERO) || (opcode == 6'h05 && ~ZERO) ? 1'b1 : 1'b0;
|
||||
|
||||
// pc_sel_2: branch if equal or not equal
|
||||
C[`pc_sel_2] = ((opcode == `OP_BEQ) && ZERO) || ((opcode == `OP_BNE) && ~ZERO);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -152,7 +152,7 @@ wire [31:0] pc_sel;
|
||||
wire [31:0] pc_branch, pc_jump, pc_sel_p1, pc_sel_p2;
|
||||
RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0));
|
||||
MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, pc_sel_1);
|
||||
RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc), .B(imm_sx), .SnA(1'b0));
|
||||
RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc_inc), .B(imm_sx), .SnA(1'b0));
|
||||
MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, pc_sel_2);
|
||||
buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr});
|
||||
MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, pc_sel_3);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user