project: more cleanup
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0361dcc161
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a7870b87eb
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E0EBF441EA424369
@ -30,8 +30,8 @@ wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
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// reset
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reg RST;
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//integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
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integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
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integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
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//integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
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// Clock generator instance
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CLK_GENERATOR clk_gen_inst(.CLK(CLK));
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123
control_unit.v
123
control_unit.v
@ -19,7 +19,7 @@
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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// Control signals, same as in data_path.v
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// Control signals, referenced in data_path.v
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`define pc_load 0
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`define pc_sel_1 1
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`define pc_sel_2 2
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@ -105,6 +105,7 @@ output READ, WRITE;
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input ZERO, CLK, RST;
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input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
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// Task to print instruction
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task print_instruction;
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input [`DATA_INDEX_LIMIT:0] inst;
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reg [5:0] opcode;
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@ -127,52 +128,46 @@ begin
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$write("@ %6dns -> [0X%08h] ", $time, inst);
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case(opcode)
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// R-Type
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6'h00 : begin
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case(funct)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd, rs, shamt);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd, rs, shamt);
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6'h08: $write("jr r[%02d];", rs);
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default: $write("");
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endcase
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end
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// R-Type
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`OP_RTYPE: case(funct)
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`FN_ADD: $write("add r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_SUB: $write("sub r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_MUL: $write("mul r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_AND: $write("and r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_OR: $write("or r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_NOR: $write("nor r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_SLT: $write("slt r[%02d], r[%02d], r[%02d];", rd, rs, rt);
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`FN_SLL: $write("sll r[%02d], r[%02d], %2d;", rd, rs, shamt);
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`FN_SRL: $write("srl r[%02d], 0X%02h, r[%02d];", rd, rs, shamt);
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`FN_JR: $write("jr r[%02d];", rs);
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default: $write("");
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endcase
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// I-type
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt, imm);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_ADDI: $write("addi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_MULI: $write("muli r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_ANDI: $write("andi r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_ORI: $write("ori r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_LUI: $write("lui r[%02d], 0X%04h;", rt, imm);
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`OP_SLTI: $write("slti r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_BEQ: $write("beq r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_BNE: $write("bne r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_LW: $write("lw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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`OP_SW: $write("sw r[%02d], r[%02d], 0X%04h;", rt, rs, imm);
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// J-Type
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6'h02 : $write("jmp 0X%07h;", addr);
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6'h03 : $write("jal 0X%07h;", addr);
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6'h1b : $write("push;");
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6'h1c : $write("pop;");
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default: $write("");
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`OP_JMP: $write("jmp 0X%07h;", addr);
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`OP_JAL: $write("jal 0X%07h;", addr);
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`OP_PUSH: $write("push;");
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`OP_POP: $write("pop;");
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default: $write("");
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endcase
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$write("\n");
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end
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endtask
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//------------------------------------- END ---------------------------------------//
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reg read, write;
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buf (READ, read);
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buf (WRITE, write);
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//assign READ = read;
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//assign WRITE = write;
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reg [31:0] C;
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@ -209,7 +204,7 @@ always @ (state) begin
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// memory
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read = 1'b1;
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write = 1'b0;
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// load data from mem[PC]
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// ma_sel_2: load data from mem[PC]
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C[`ma_sel_2] = 1'b1;
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end
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// decode - parse instruction and read values from register file
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@ -226,8 +221,8 @@ always @ (state) begin
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print_instruction(INSTRUCTION);
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// loaded in previous state, set to 0
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C[`ir_load] = 1'b0;
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// load now
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C[`sp_load] = opcode == `OP_POP; // sp is decremented before pop
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// load now - sp is incremented before pop
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C[`sp_load] = opcode == `OP_POP;
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// r1_sel_1: rs by default (0), push - r1 (1)
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C[`r1_sel_1] = opcode == `OP_PUSH;
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@ -247,9 +242,9 @@ always @ (state) begin
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C[`pc_sel_3] = ~(opcode == `OP_JMP || opcode == `OP_JAL);
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// alu_oprn - operation to be performed by ALU
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// R-type
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if (opcode == `OP_RTYPE) begin
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case (funct)
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case (opcode)
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// R-type
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`OP_RTYPE: case (funct)
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`FN_ADD: C[`alu_oprn] = `ALU_ADD;
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`FN_SUB: C[`alu_oprn] = `ALU_SUB;
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`FN_MUL: C[`alu_oprn] = `ALU_MUL;
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@ -261,26 +256,22 @@ always @ (state) begin
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`FN_SLT: C[`alu_oprn] = `ALU_SLT;
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// I-type and J-type
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else begin
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case (opcode)
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// I-type
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`OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi
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`OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli
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`OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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// J-type
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`OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// I-type
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`OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi
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`OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli
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`OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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// J-type
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`OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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// op1_sel_1: r1 by default (0), push or pop - sp (1)
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C[`op1_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP;
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@ -290,7 +281,7 @@ always @ (state) begin
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// ('nor' not availble in I-type)
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C[`op2_sel_2] = ~(opcode == `OP_ANDI || opcode == `OP_ORI);
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// op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift or inc/dec (1)
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// (inc/dec is for sp with push or pop)
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// (inc/dec is for sp with pop or push)
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C[`op2_sel_3] = opcode == `OP_RTYPE || opcode == `OP_PUSH || opcode == `OP_POP;
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// op2_sel_4: op2_sel_3 for I-type (except beq, bne) or R-type shift or inc/dec (0), else r2 (1)
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// i.e. r2 if R-type (except sll/srl), or bne/beq
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@ -321,13 +312,14 @@ always @ (state) begin
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read = opcode == `OP_POP || opcode == `OP_LW;
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end
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`PROC_WB: begin
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// load now
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C[`sp_load] = opcode == `OP_PUSH; // sp is incremented after push
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// loaded in previous state, set to 0
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read = 1'b0;
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write = 1'b0;
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// load now
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// pc gets next instruction address
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C[`pc_load] = 1'b1;
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// sp is decremented after push
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C[`sp_load] = opcode == `OP_PUSH;
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// write to register file if
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// R-type (except jr) or I-type (except beq, bne, sw) or pop or jal
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C[`reg_w] = (opcode == `OP_RTYPE && funct != `FN_JR) // R-type (except jr)
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@ -335,7 +327,6 @@ always @ (state) begin
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|| opcode == `OP_LUI || opcode == `OP_SLTI || opcode == `OP_LW) // I-type (except beq, bne, sw)
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|| (opcode == `OP_POP || opcode == `OP_JAL) // pop or jal
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;
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// selections
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// pc_sel_2: branch if equal or not equal
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C[`pc_sel_2] = ((opcode == `OP_BEQ) && ZERO) || ((opcode == `OP_BNE) && ~ZERO);
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end
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