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implement a Verilog gate level model for ripple carry adder subtractor

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Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
This commit is contained in:
Iurii Tatishchev 2024-10-01 20:42:02 -07:00
parent d1475b5a4f
commit 3801d523de
Signed by: CaZzzer
GPG Key ID: 28BE602058C08557
3 changed files with 7 additions and 27 deletions
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12
full_adder.v
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@ -23,19 +23,9 @@ module FULL_ADDER(S,CO,A,B, CI);
output S,CO;
input A,B, CI;
// half adder 1
//assign Y = A ^ B;
//assign CO1 = A & B;
// half adder 2
//assign S = Y ^ CI;
//assign CO2 = Y & CI;
//assign CO = CO1 | CO2;
wire Y, CO1, CO2;
HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
assign CO = CO1 | CO2;
or (CO, CO1, CO2);
endmodule

9
half_adder.v
View File

@ -22,12 +22,7 @@ module HALF_ADDER(Y,C,A,B);
output Y,C;
input A,B;
// this
assign Y = A ^ B;
assign C = A & B;
// or this
//xor digit(Y, A, B);
//and carry(C, A, B);
xor digit(Y, A, B);
and carry(C, A, B);
endmodule

13
rc_add_sub_32.v
View File

@ -42,15 +42,9 @@ input [`DATA_INDEX_LIMIT:0] A;
input [`DATA_INDEX_LIMIT:0] B;
input SnA;
//wire C0, C1, C2, C3;
//assign C0 = SnA;
//FULL_ADDER b0(Y[0], C1, A[0], B[0], C0);
// module FULL_ADDER(S,CO,A,B, CI);
// carry-in bits for each 1 bit full adder
// carry-in bits for each 1-bit full adder
wire C[0:32];
assign C[0] = SnA;
buf (C[0], SnA);
genvar i;
generate
@ -60,6 +54,7 @@ generate
end
endgenerate
assign CO = C[32];
//assign CO = C[32];
buf (CO, C[32]);
endmodule