lab-08: gate level model for 32x32-bit register file
Gate level implementation for the following components: - DECODER_5x32 - MUX32_32x1 - REGISTER_FILE_32x32 Additional tests added in register file testbench.
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@ -68,24 +68,43 @@ no_of_pass = 0;
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// Write cycle
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for(i=0;i<32; i = i + 1)
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begin
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#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
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#10 DATA_REG = i * 10; READ=1'b0; WRITE=1'b1; ADDR_W = i;
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end
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#5 READ=1'b0; WRITE=1'b0;
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// test of write data
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for(i=0;i<32; i = i + 1)
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begin
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#5 READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
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#5 READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i % 7;
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#5 no_of_test = no_of_test + 1;
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if (DATA_R1 !== i)
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$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
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else
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if (DATA_R1 !== i * 10)
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$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 10, DATA_R1);
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else if (DATA_R2 !== (i % 7) * 10)
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$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, (i % 7) * 10, DATA_R2);
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else
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no_of_pass = no_of_pass + 1;
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result[ridx] = DATA_R1; ridx=ridx+1;
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result[ridx] = DATA_R1; ridx=ridx+1;
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end
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// Testing read and write at the same time
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for(i=2;i<16; i = i + 1)
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begin
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#5 DATA_REG = 20; READ=1'b1; WRITE=1'b1; ADDR_W = i + 1; ADDR_R1 = i; ADDR_R2 = i * 2;
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#5 no_of_test = no_of_test + 1;
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if (DATA_R1 !== 20)
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$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, 20, DATA_R1);
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else if (DATA_R2 !== i * 20)
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$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 20, DATA_R2);
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else
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no_of_pass = no_of_pass + 1;
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result[ridx] = DATA_R1; ridx=ridx+1;
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result[ridx] = DATA_R1; ridx=ridx+1;
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end
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// TODO: Read and write from the same address at the same time?
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#5 READ=1'b0; WRITE=1'b0; // No op
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