lab-05: gate level model for 32-bit barrel shifter

Gate level implementation for the following components:
- SHIFT32_L
- SHIFT32_R
- BARREL_SHIFTER32
- SHIFT32

barrel_shifter.v

@@ -21,7 +21,21 @@ input [31:0] D;
 input [31:0] S;
 input LnR;
 
-// TBD
+// check if upper bits are nonzero
+wire oob [31:5];
+buf (oob[5], S[5]);
+genvar i;
+generate
+    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
+        or (oob[i], oob[i-1], S[i]);
+    end
+endgenerate
+
+wire [31:0] shifted;
+BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
+
+// return 0 if S >= 32
+MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
 
 endmodule
 
@@ -34,7 +48,11 @@ input [31:0] D;
 input [4:0] S;
 input LnR;
 
-// TBD
+wire [31:0] shifters [1:0];
+SHIFT32_R shifter_r(shifters[0], D, S);
+SHIFT32_L shifter_l(shifters[1], D, S);
+
+MUX32_2x1 mux_lnr(Y, shifters[0], shifters[1], LnR);
 
 endmodule
 
@@ -46,7 +64,22 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-// TBD
+wire [31:0] stages [5:0];
+buf stage0[31:0] (stages[0], D);
+
+genvar i, j;
+generate
+    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
+        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
+            if (j < 32 - (2 ** i))
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j + (2 ** i)], S[i]);
+            else
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
+        end
+    end
+endgenerate
+
+buf out[31:0] (Y, stages[5]);
 
 endmodule
 
@@ -58,7 +91,22 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-// TBD
+
+wire [31:0] stages [5:0];
+buf stage0[31:0] (stages[0], D);
+
+genvar i, j;
+generate
+    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
+        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
+            if (j >= (2 ** i))
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j - (2 ** i)], S[i]);
+            else
+                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
+        end
+    end
+endgenerate
+
+buf out[31:0] (Y, stages[5]);
 
 endmodule
-