(WIP): REG1

2024-10-19 15:54:51 -07:00 · 2024-10-19 15:54:51 -07:00 · a110f7c042
commit a110f7c042
parent 7c0645eaa1
1 changed files with 4 additions and 1 deletions
--- a/logic.v
+++ b/logic.v
@ -56,7 +56,10 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;

-// TBD
+wire D_out;
+MUX1_2x1 data(D_out, Q, D, L);
+
+D_FF dff(Q, Qbar, D_out, C, nP, nR);

 endmodule