control unit: progress
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160
control_unit.v
160
control_unit.v
@ -55,6 +55,7 @@
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`define wa_sel_3 28
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// ALU operation codes
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`define ALU_NOP 6'h00
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`define ALU_ADD 6'h01
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`define ALU_SUB 6'h02
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`define ALU_MUL 6'h03
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@ -66,6 +67,7 @@
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`define ALU_SLT 6'h09
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// Instruction opcodes
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// R-type
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`define OP_RTYPE 6'h00
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`define FN_ADD 6'h20
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`define FN_SUB 6'h22
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@ -77,7 +79,7 @@
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`define FN_SLL 6'h01
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`define FN_SRL 6'h02
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`define FN_JR 6'h08
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// I-type
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`define OP_ADDI 6'h08
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`define OP_MULI 6'h1d
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`define OP_ANDI 6'h0c
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@ -88,6 +90,11 @@
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`define OP_BNE 6'h05
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`define OP_LW 6'h23
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`define OP_SW 6'h2b
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// J-type
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`define OP_JMP 6'h02
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`define OP_JAL 6'h03
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`define OP_PUSH 6'h1b
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`define OP_POP 6'h1c
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module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
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// Output signals
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@ -121,39 +128,38 @@ $write("@ %6dns -> [0X%08h] ", $time, inst);
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case(opcode2)
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// R-Type
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6'h00 : begin
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case(funct2)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
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6'h08: $write("jr r[%02d];", rs2);
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default: begin $write("");
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end
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endcase
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end
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// I-type
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt2, immediate2);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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// J-Type
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6'h02 : $write("jmp 0X%07h;", address2);
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6'h03 : $write("jal 0X%07h;", address2);
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6'h1b : $write("push;");
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6'h1c : $write("pop;");
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default: $write("");
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6'h00 : begin
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case(funct2)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
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6'h08: $write("jr r[%02d];", rs2);
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default: $write("");
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endcase
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end
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// I-type
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt2, immediate2);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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// J-Type
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6'h02 : $write("jmp 0X%07h;", address2);
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6'h03 : $write("jal 0X%07h;", address2);
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6'h1b : $write("push;");
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6'h1c : $write("pop;");
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default: $write("");
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endcase
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$write("\n");
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@ -209,33 +215,27 @@ always @ (state) begin
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case (state)
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// fetch - next instruction from memory at PC
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`PROC_FETCH: begin
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print_instruction(INSTRUCTION);
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// set everything in ctrl to 0
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C = 32'b0;
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// loaded in previous state, set to 0
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C[`pc_load] = 1'b0;
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C[`ir_load] = 1'b0;
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C[`sp_load] = 1'b0;
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C[`reg_r] = 1'b0;
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C[`reg_w] = 1'b0;
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// load now
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// memory
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read = 1'b1;
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write = 1'b0;
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// selections
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// ma_sel_2 - load data from mem[PC]
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C[`ma_sel_1] = 1'b0;
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C[`ma_sel_2] = 1'b1;
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C[`ma_sel_2] = 1'b1; // load data from mem[PC]
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end
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// decode - parse instruction and read values from register file
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`PROC_DECODE: begin
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// loaded in previous state, set to 0
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C[`sp_load] = 1'b0;
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read = 1'b0;
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// load now
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C[`ir_load] = 1'b1;
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C[`reg_r] = 1'b1;
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C[`reg_w] = 1'b0;
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end
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// execute - perform operation based on instruction
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`PROC_EXE: begin
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print_instruction(INSTRUCTION);
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// loaded in previous state, set to 0
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C[`ir_load] = 1'b0;
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// selections
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// r1_sel_1: push - store value of r0 at stack pointer
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C[`r1_sel_1] = opcode != 6'h1b ? 1'b0 : 1'b1;
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@ -251,41 +251,41 @@ always @ (state) begin
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// TODO: this should only be selected if the condition is met
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// pc_sel_2 = opcode == 6'h04 || opcode == 6'h05 ? 1'b1 : 1'b0;
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// jmp, jal - jump to address
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C[`pc_sel_3] = opcode == 6'h02 || opcode == 6'h03 ? 1'b0 : 1'b1;
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C[`pc_sel_3] = opcode == `OP_JMP || opcode == `OP_JAL ? 1'b0 : 1'b1;
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// alu_oprn - operation to be performed by ALU
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// R-type
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if (opcode == 6'h00) begin
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if (opcode == `OP_RTYPE) begin
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case (funct)
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6'h20: C[`alu_oprn] = `ALU_ADD;
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6'h22: C[`alu_oprn] = `ALU_SUB;
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6'h2c: C[`alu_oprn] = `ALU_MUL;
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6'h02: C[`alu_oprn] = `ALU_SRL;
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6'h01: C[`alu_oprn] = `ALU_SLL;
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6'h24: C[`alu_oprn] = `ALU_AND;
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6'h25: C[`alu_oprn] = `ALU_OR;
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6'h27: C[`alu_oprn] = `ALU_NOR;
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6'h2a: C[`alu_oprn] = `ALU_SLT;
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default: C[`alu_oprn] = 6'h00;
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`FN_ADD: C[`alu_oprn] = `ALU_ADD;
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`FN_SUB: C[`alu_oprn] = `ALU_SUB;
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`FN_MUL: C[`alu_oprn] = `ALU_MUL;
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`FN_SRL: C[`alu_oprn] = `ALU_SRL;
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`FN_SLL: C[`alu_oprn] = `ALU_SLL;
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`FN_AND: C[`alu_oprn] = `ALU_AND;
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`FN_OR: C[`alu_oprn] = `ALU_OR;
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`FN_NOR: C[`alu_oprn] = `ALU_NOR;
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`FN_SLT: C[`alu_oprn] = `ALU_SLT;
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// I-type and J-type
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else begin
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case (opcode)
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// I-type
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6'h08: C[`alu_oprn] = `ALU_ADD; // addi
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6'h1d: C[`alu_oprn] = `ALU_MUL; // muli
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6'h0c: C[`alu_oprn] = `ALU_AND; // andi
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6'h0d: C[`alu_oprn] = `ALU_OR; // ori
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6'h0a: C[`alu_oprn] = `ALU_SLT; // slti
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6'h04: C[`alu_oprn] = `ALU_SUB; // beq - sub
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6'h05: C[`alu_oprn] = `ALU_SUB; // bne - sub
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6'h23: C[`alu_oprn] = `ALU_ADD; // lw - add
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6'h2b: C[`alu_oprn] = `ALU_ADD; // sw - add
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`OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi
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`OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli
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`OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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// J-type
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6'h1b: C[`alu_oprn] = `ALU_SUB; // push - sub
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6'h1c: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = 6'h00;
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`OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// op1_sel_1 - select r1 or sp based on opcode
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@ -304,12 +304,7 @@ always @ (state) begin
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// I-type or shift or inc/dec - op2_sel_3, else r2
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// i.e. r2 only if R-type and not shift
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C[`op2_sel_4] = opcode != 6'h00 || C[`alu_oprn] == 6'h04 || C[`alu_oprn] == 6'h05 ? 1'b0 : 1'b1;
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end
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// execute - perform operation based on instruction
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`PROC_EXE: begin
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// loaded in previous state, set to 0
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C[`ir_load] = 1'b0;
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// selections
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// wd_sel_1 - alu_out or DATA_IN
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C[`wd_sel_1] = 1'b0;
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// wd_sel_2 - wd_sel_1 or imm_zx_lsb
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@ -329,8 +324,8 @@ always @ (state) begin
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write = 1'b1;
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end
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else begin
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read = 1'b1;
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write = 1'b0;
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// read = 1'b1;
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// write = 1'b0;
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end
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end
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`PROC_WB: begin
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@ -347,16 +342,12 @@ always @ (state) begin
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|| (opcode == 6'h1c || opcode == 6'h03) // pop or jal
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? 1'b1 : 1'b0;
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// selections
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// ma_sel_2 - load data from mem[PC]
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C[`ma_sel_2] = 1'b1;
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// pc_sel_2 - branch if equal or not equal
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C[`pc_sel_2] = (opcode == 6'h04 && ZERO) || (opcode == 6'h05 && ~ZERO) ? 1'b1 : 1'b0;
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end
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endcase
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end
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endmodule
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@ -404,5 +395,4 @@ always @ (posedge CLK) begin
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end
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assign STATE = state_sel;
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endmodule
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@ -149,11 +149,11 @@ ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(alu
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// Progam Counter Input
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wire [31:0] pc_sel;
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wire [31:0] pc_offset, pc_jump, pc_sel_p1, pc_sel_p2;
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wire [31:0] pc_branch, pc_jump, pc_sel_p1, pc_sel_p2;
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RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0));
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MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, pc_sel_1);
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RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_offset), .CO(), .A(pc), .B(imm_sx), .SnA(1'b0));
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MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_offset, pc_sel_2);
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RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc), .B(imm_sx), .SnA(1'b0));
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MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, pc_sel_2);
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buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr});
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MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, pc_sel_3);
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// Program Counter
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