(WIP): SR Latch

2024-10-19 15:20:23 -07:00 · 2024-10-19 15:20:23 -07:00 · d217faf166
commit d217faf166
parent 8dbdebb9ce
1 changed files with 7 additions and 1 deletions
--- a/logic.v
+++ b/logic.v
@ -95,7 +95,13 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;

-// TBD
+wire r1, r2;
+
+nand n1(r1, C, S);
+nand n2(r2, C, R);
+
+nand n3(Q, nP, r1, Qbar);
+nand n4(Qbar, nR, r2, Q);

 endmodule