a7870b87eb
project: more cleanup
2024-11-24 01:14:12 -08:00
0361dcc161
project: some cleanup
2024-11-20 02:01:20 -08:00
ceba9d6fd5
control unit: fix jal, add comprehensive instruction test
2024-11-20 00:55:20 -08:00
0198e8be41
control unit: fix stack pointer inc/dec, passing SP15, FL15, RevFib
2024-11-18 23:00:06 -08:00
507fa2e863
control unit: passing SP15 and SP17
2024-11-18 22:18:26 -08:00
b651f04748
control unit: more progress, fibonacci working
2024-11-18 00:47:16 -08:00
2ffd8c9424
da vinci tb: patch for smaller (20-bit) memory for faster tests
2024-11-18 00:46:22 -08:00
05c950a0f8
control unit: progress
2024-11-17 04:19:03 -08:00
5d64b65212
data path: replace instruction register with D-latch
2024-11-17 02:38:11 -08:00
9e6d1d5df2
control unit: ctrl signal refactor
2024-11-17 02:30:25 -08:00
1e1d0f0e05
project: track output
2024-11-17 01:14:29 -08:00
8810726d65
project: minor refactors
2024-11-17 00:44:08 -08:00
c8baf4262a
project: edit ctrl signal to match doc
2024-11-16 23:54:09 -08:00
02781c283f
project: add da vinci test programs
2024-11-16 16:49:44 -08:00
88b635122f
(WIP) control unit: initial implementation of things
2024-11-12 18:02:06 -08:00
d10a3d6130
data path: fix port connection warnings
2024-11-12 13:38:37 -08:00
a2d547df45
data path: initial gate level implementation
2024-11-12 13:12:58 -08:00
ff1c1630b2
data path: add initial wires and buffers
2024-11-12 13:12:58 -08:00
ff6e7792f4
misc: fix unconnected port warnings for ALU and TWOSCOMP
2024-11-12 13:11:48 -08:00
9584db84fd
logic: add 32-bit register with parameterized preset pattern
2024-11-12 13:11:45 -08:00
dbc23d80e4
lab-08: fix register file - disable writing when WRITE=0
2024-10-24 23:11:59 -07:00
c3da7787d3
lab-08: fix HiZ on register file when READ=0
2024-10-24 12:35:34 -07:00
eca53c1104
lab-08: gate level model for 32x32-bit register file
...
Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32
Additional tests added in register file testbench.
2024-10-19 18:39:35 -07:00
3091103f81
lab-07: gate level model for 32-bit register
...
Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32
2024-10-19 18:39:30 -07:00
cce0c524d9
lab-06: gate level model for Arithmetic & Logic Unit
...
Gate level implementation for the following components:
- ALU
- MUX32_16x1
2024-10-19 18:39:23 -07:00
1ab4ea027d
lab-05: gate level model for 32-bit barrel shifter
...
Gate level implementation for the following components:
- SHIFT32_L
- SHIFT32_R
- BARREL_SHIFTER32
- SHIFT32
2024-10-19 18:39:16 -07:00
5a4b5a312a
lab-04: gate level model for 32-bit signed multiplier
...
Gate level implementation for the following components:
- MULT32_U
- MULT32
- MUX32_2x1
2024-10-19 18:39:02 -07:00
597e245641
lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement
...
Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
2024-10-03 21:30:23 -07:00
42732e4fe0
lab-02: gate level model for ripple carry adder subtractor
...
Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
2024-10-03 21:30:09 -07:00
87e48f162e
implement a Verilog gate level model for 32-bit basic logic gates
...
Gate level implementation for the following components:
- NOR32_2x1
- AND32_2x1
- INV32_1x1
- OR32_2x1
2024-10-01 10:44:45 -07:00
5520d6d716
initial commit
2024-10-01 10:39:56 -07:00
