Yuri Tatishchev cce0c524d9

lab-06: gate level model for Arithmetic & Logic Unit ...

Gate level implementation for the following components:
- ALU
- MUX32_16x1

2024-10-19 18:39:23 -07:00

DOC

initial commit

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GOLDEN

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TESTBENCH

lab-04: gate level model for 32-bit signed multiplier

2024-10-19 18:39:02 -07:00

.gitignore

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alu.v

lab-06: gate level model for Arithmetic & Logic Unit

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barrel_shifter.v

lab-05: gate level model for 32-bit barrel shifter

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clk_gen.v

initial commit

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control_unit.v

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da_vinci.v

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data_path.v

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full_adder.v

lab-02: gate level model for ripple carry adder subtractor

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half_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

logic_32_bit.v

lab-04: gate level model for 32-bit signed multiplier

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logic.v

lab-06: gate level model for Arithmetic & Logic Unit

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memory.v

initial commit

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mult.v

lab-04: gate level model for 32-bit signed multiplier

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mux.v

lab-06: gate level model for Arithmetic & Logic Unit

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prj_definition.v

initial commit

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processor.v

initial commit

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rc_add_sub_32.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

register_file.v

initial commit

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Description

CS147DV instruction set implementation in Verilog

348 KiB

Languages

Verilog 96%

Coq 4%