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lab-04: gate level model for 32-bit signed multiplier

Gate level implementation for the following components:
- MULT32_U
- MULT32
- MUX32_2x1

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DOC

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GOLDEN

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TESTBENCH

lab-04: gate level model for 32-bit signed multiplier

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.gitignore

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alu.v

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barrel_shifter.v

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clk_gen.v

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control_unit.v

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da_vinci.v

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data_path.v

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full_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

half_adder.v

lab-02: gate level model for ripple carry adder subtractor

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logic_32_bit.v

lab-04: gate level model for 32-bit signed multiplier

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logic.v

lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

2024-10-03 21:30:23 -07:00

memory.v

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mult.v

lab-04: gate level model for 32-bit signed multiplier

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mux.v

lab-04: gate level model for 32-bit signed multiplier

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prj_definition.v

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processor.v

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rc_add_sub_32.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

register_file.v

initial commit

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