Yuri Tatishchev ff1c1630b2 data path: add initial wires and buffers

2024-11-12 13:12:58 -08:00

DOC

initial commit

2024-10-01 10:39:56 -07:00

GOLDEN

initial commit

2024-10-01 10:39:56 -07:00

TESTBENCH

lab-08: fix register file - disable writing when WRITE=0

2024-10-24 23:11:59 -07:00

.gitignore

initial commit

2024-10-01 10:39:56 -07:00

alu.v

misc: fix unconnected port warnings for ALU and TWOSCOMP

2024-11-12 13:11:48 -08:00

barrel_shifter.v

lab-05: gate level model for 32-bit barrel shifter

2024-10-19 18:39:16 -07:00

clk_gen.v

initial commit

2024-10-01 10:39:56 -07:00

control_unit.v

initial commit

2024-10-01 10:39:56 -07:00

da_vinci.v

initial commit

2024-10-01 10:39:56 -07:00

data_path.v

data path: add initial wires and buffers

2024-11-12 13:12:58 -08:00

full_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

half_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

logic_32_bit.v

lab-04: gate level model for 32-bit signed multiplier

2024-10-19 18:39:02 -07:00

logic.v

misc: fix unconnected port warnings for ALU and TWOSCOMP

2024-11-12 13:11:48 -08:00

memory.v

initial commit

2024-10-01 10:39:56 -07:00

mult.v

lab-04: gate level model for 32-bit signed multiplier

2024-10-19 18:39:02 -07:00

mux.v

lab-07: gate level model for 32-bit register

2024-10-19 18:39:30 -07:00

prj_definition.v

initial commit

2024-10-01 10:39:56 -07:00

processor.v

initial commit

2024-10-01 10:39:56 -07:00

rc_add_sub_32.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

register_file.v

lab-08: fix register file - disable writing when WRITE=0

2024-10-24 23:11:59 -07:00

Description

CS147DV instruction set implementation in Verilog

348 KiB

Languages

Verilog 96%

Coq 4%