c3da7787d3
lab-08: fix HiZ on register file when READ=0
2024-10-24 12:35:34 -07:00
eca53c1104
lab-08: gate level model for 32x32-bit register file
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Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32
Additional tests added in register file testbench.
2024-10-19 18:39:35 -07:00
3091103f81
lab-07: gate level model for 32-bit register
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Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32
2024-10-19 18:39:30 -07:00
cce0c524d9
lab-06: gate level model for Arithmetic & Logic Unit
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Gate level implementation for the following components:
- ALU
- MUX32_16x1
2024-10-19 18:39:23 -07:00
1ab4ea027d
lab-05: gate level model for 32-bit barrel shifter
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Gate level implementation for the following components:
- SHIFT32_L
- SHIFT32_R
- BARREL_SHIFTER32
- SHIFT32
2024-10-19 18:39:16 -07:00
5a4b5a312a
lab-04: gate level model for 32-bit signed multiplier
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Gate level implementation for the following components:
- MULT32_U
- MULT32
- MUX32_2x1
2024-10-19 18:39:02 -07:00
597e245641
lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement
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Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
2024-10-03 21:30:23 -07:00
42732e4fe0
lab-02: gate level model for ripple carry adder subtractor
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Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
2024-10-03 21:30:09 -07:00
87e48f162e
implement a Verilog gate level model for 32-bit basic logic gates
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Gate level implementation for the following components:
- NOR32_2x1
- AND32_2x1
- INV32_1x1
- OR32_2x1
2024-10-01 10:44:45 -07:00
5520d6d716
initial commit
2024-10-01 10:39:56 -07:00
