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Author	SHA1	Message	Date
CaZzzer	41ecb62082	lab-07: gate level model for 32-bit register ... Gate level implementation for the following components: - SR_LATCH - D_LATCH - D_FF - REG1 - REG32	2024-10-19 16:05:17 -07:00
CaZzzer	a110f7c042	(WIP): REG1	2024-10-19 15:54:51 -07:00
CaZzzer	7c0645eaa1	(WIP): D Latch and D FlipFlop	2024-10-19 15:47:35 -07:00
CaZzzer	d217faf166	(WIP): SR Latch	2024-10-19 15:20:23 -07:00
CaZzzer	8dbdebb9ce	lab-06: gate level model for Arithmetic & Logic Unit ... Gate level implementation for the following components: - ALU - MUX32_16x1	2024-10-10 19:00:03 -07:00
CaZzzer	800b80ef85	lab-06 (WIP): mux32_16x1 working	2024-10-10 15:14:25 -07:00
CaZzzer	585d9713d2	lab-05: gate level model for 32-bit barrel shifter ... Gate level implementation for the following components: - SHIFT32_L - SHIFT32_R - BARREL_SHIFTER32 - SHIFT32	2024-10-10 13:31:00 -07:00
CaZzzer	cdfaa51626	lab-04: signed mult working	2024-10-08 16:00:01 -07:00
CaZzzer	73aa647c9b	lab-04 (WIP): unsigned mult working	2024-10-08 14:48:44 -07:00
CaZzzer	6fa94cfe59	lab-04 (WIP): mux implementation	2024-10-08 00:05:19 -07:00
CaZzzer	597e245641	lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement ... Gate level implementation for the following components: - RC_ADD_SUB_64 - TWOSCOMP64 - TWOSCOMP32	2024-10-03 21:30:23 -07:00
CaZzzer	42732e4fe0	lab-02: gate level model for ripple carry adder subtractor ... Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32	2024-10-03 21:30:09 -07:00
CaZzzer	87e48f162e	implement a Verilog gate level model for 32-bit basic logic gates ... Gate level implementation for the following components: - NOR32_2x1 - AND32_2x1 - INV32_1x1 - OR32_2x1	2024-10-01 10:44:45 -07:00
CaZzzer	5520d6d716	initial commit	2024-10-01 10:39:56 -07:00