CaZzzer cdfaa51626 lab-04: signed mult working

2024-10-08 16:00:01 -07:00

DOC

initial commit

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GOLDEN

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TESTBENCH

lab-04 (WIP): unsigned mult working

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.gitignore

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alu.v

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barrel_shifter.v

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clk_gen.v

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control_unit.v

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da_vinci.v

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data_path.v

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full_adder.v

lab-02: gate level model for ripple carry adder subtractor

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half_adder.v

lab-02: gate level model for ripple carry adder subtractor

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logic_32_bit.v

lab-04 (WIP): unsigned mult working

2024-10-08 14:48:44 -07:00

logic.v

lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

2024-10-03 21:30:23 -07:00

memory.v

initial commit

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mult.v

lab-04: signed mult working

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mux.v

lab-04 (WIP): mux implementation

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prj_definition.v

initial commit

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processor.v

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rc_add_sub_32.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

register_file.v

initial commit

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S

Description

CS147DV instruction set implementation in Verilog

348 KiB

Languages

Verilog 96.1%

Coq 3.9%