lab-08: fix HiZ on register file when READ=0

Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32

Additional tests added in register file testbench.

TESTBENCH/register_file_tb.v

@@ -84,7 +84,6 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
@@ -100,10 +99,20 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
 
 end
 
+// Test reading when READ=0
+#5     READ=1'b0;
+#5     no_of_test = no_of_test + 1;
+if (DATA_R1 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
+else if (DATA_R2 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
+else
+no_of_pass  = no_of_pass + 1;
+result[ridx] = DATA_R1; ridx=ridx+1;
+
 // TODO: Read and write from the same address at the same time?
 
 #5    READ=1'b0; WRITE=1'b0; // No op

register_file.v

@@ -41,31 +41,27 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// module REG32(Q, D, LOAD, CLK, RESET);
-// module DECODER_5x32(D,I);
-
-// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
-                     // I8, I9, I10, I11, I12, I13, I14, I15,
-                     // I16, I17, I18, I19, I20, I21, I22, I23,
-                     // I24, I25, I26, I27, I28, I29, I30, I31, S);
-
 wire [31:0] Q [31:0];
-wire [31:0] write;
-DECODER_5x32 d_write(write, ADDR_W);
+wire [31:0] r_write;
+DECODER_5x32 d_write(r_write, ADDR_W);
 
-REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
+REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
 
-MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+wire [31:0] r1, r2;
+MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R1
 );
-MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R2
 );
 
+MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
+MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
+
 endmodule