CaZzzer 171a6d1f77 lab-08: fix HiZ on register file when READ=0

2024-10-24 12:33:13 -07:00

DOC

initial commit

2024-10-01 10:39:56 -07:00

GOLDEN

initial commit

2024-10-01 10:39:56 -07:00

TESTBENCH

lab-08: fix HiZ on register file when READ=0

2024-10-24 12:33:13 -07:00

.gitignore

initial commit

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alu.v

lab-06: gate level model for Arithmetic & Logic Unit

2024-10-10 19:00:03 -07:00

barrel_shifter.v

lab-05: gate level model for 32-bit barrel shifter

2024-10-10 13:31:00 -07:00

clk_gen.v

initial commit

2024-10-01 10:39:56 -07:00

control_unit.v

initial commit

2024-10-01 10:39:56 -07:00

da_vinci.v

initial commit

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data_path.v

initial commit

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full_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

half_adder.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

logic_32_bit.v

lab-04 (WIP): unsigned mult working

2024-10-08 14:48:44 -07:00

logic.v

(WIP) lab-08: Decoder_5x32, Mux32_32x1

2024-10-19 16:51:30 -07:00

memory.v

initial commit

2024-10-01 10:39:56 -07:00

mult.v

lab-04: signed mult working

2024-10-08 16:00:01 -07:00

mux.v

(WIP) lab-08: Decoder_5x32, Mux32_32x1

2024-10-19 16:51:30 -07:00

prj_definition.v

initial commit

2024-10-01 10:39:56 -07:00

processor.v

initial commit

2024-10-01 10:39:56 -07:00

rc_add_sub_32.v

lab-02: gate level model for ripple carry adder subtractor

2024-10-03 21:30:09 -07:00

register_file.v

lab-08: fix HiZ on register file when READ=0

2024-10-24 12:33:13 -07:00

S

Description

CS147DV instruction set implementation in Verilog

348 KiB

Languages

Verilog 96.1%

Coq 3.9%