lab-08: fix HiZ on register file when READ=0

Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32

Additional tests added in register file testbench.

TESTBENCH/register_file_tb.v

@@ -68,24 +68,52 @@ no_of_pass = 0;
 // Write cycle
 for(i=0;i<32; i = i + 1)
 begin
-#10     DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
+#10     DATA_REG = i * 10; READ=1'b0; WRITE=1'b1; ADDR_W = i;
 end
 
 #5 READ=1'b0; WRITE=1'b0;
 // test of write data
 for(i=0;i<32; i = i + 1)
 begin
-#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
+#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i % 7;
 #5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== i)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
-        else 
+        if (DATA_R1 !== i * 10)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 10, DATA_R1);
+        else if (DATA_R2 !== (i % 7) * 10)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, (i % 7) * 10, DATA_R2);
+        else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
+// Testing read and write at the same time
+for(i=2;i<16; i = i + 1)
+begin
+#5      DATA_REG = 20; READ=1'b1; WRITE=1'b1; ADDR_W = i + 1; ADDR_R1 = i; ADDR_R2 = i * 2;
+#5      no_of_test = no_of_test + 1;
+        if (DATA_R1 !== 20)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, 20, DATA_R1);
+        else if (DATA_R2 !== i * 20)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 20, DATA_R2);
+        else
+	    no_of_pass  = no_of_pass + 1;
+        result[ridx] = DATA_R1; ridx=ridx+1;
+
+end
+
+// Test reading when READ=0
+#5     READ=1'b0;
+#5     no_of_test = no_of_test + 1;
+if (DATA_R1 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
+else if (DATA_R2 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
+else
+no_of_pass  = no_of_pass + 1;
+result[ridx] = DATA_R1; ridx=ridx+1;
+
+// TODO: Read and write from the same address at the same time?
 
 #5    READ=1'b0; WRITE=1'b0; // No op
 

alu.v

@@ -31,7 +31,56 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;
 
-// TBD
+wire [31:0] res,
+            res_addsub, res_slt,
+            res_shift,
+            res_mul,
+            res_and, res_or, res_nor;
 
+// add = xx0001
+// sub = xx0010
+// slt = xx1001
+//         ^ ^ these bits
+// can use oprn[1] or oprn[3] for SnA
+wire SnA;
+or (SnA, OPRN[1], OPRN[3]);
+RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
+buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
+
+// shift_r = xx0100
+// shift_l = xx0101
+//                ^ this bit
+// can use oprn[0] for LnR
+SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
+
+// mul = xx0011
+MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
+
+// and = xx0110
+// or  = xx0111
+// nor = xx1000
+AND32_2x1 and32(res_and, OP1, OP2);
+OR32_2x1 or32(res_or, OP1, OP2);
+NOR32_2x1 nor32(res_nor, OP1, OP2);
+
+MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
+               .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
+               .I4(res_shift),.I5(res_shift),
+               .I6(res_and), .I7(res_or), .I8(res_nor),
+               .I9(res_slt)
+);
+
+// or bits of result for zero flag
+wire nzf [31:0];
+buf (nzf[0], res[0]);
+genvar i;
+generate
+    for (i = 1; i < 32; i = i + 1) begin : zf_gen
+        or (nzf[i], nzf[i-1], res[i]);
+    end
+endgenerate
+
+not (ZERO, nzf[31]);
+buf res_out [31:0] (OUT, res);
 
 endmodule

logic.v

@@ -43,7 +43,12 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-// TBD
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1) begin : reg_gen
+        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
+    end
+endgenerate
 
 endmodule
 
@@ -56,7 +61,10 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire D_out;
+MUX1_2x1 data(D_out, Q, D, L);
+
+D_FF dff(Q, Qbar, D_out, C, nP, nR);
 
 endmodule
 
@@ -69,7 +77,11 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire Cbar, Y, Ybar;
+not C_inv(Cbar, C);
+D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
+
+SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
 
 endmodule
 
@@ -82,7 +94,10 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire Dbar;
+not D_inv(Dbar, D);
+
+SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
 
 endmodule
 
@@ -95,7 +110,13 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire r1, r2;
+
+nand n1(r1, C, S);
+nand n2(r2, C, R);
+
+nand n3(Q, nP, r1, Qbar);
+nand n4(Qbar, nR, r2, Q);
 
 endmodule
 
@@ -106,7 +127,19 @@ output [31:0] D;
 // input
 input [4:0] I;
 
-// TBD
+wire [15:0] half;
+wire I_not;
+not I_inv(I_not, I[4]);
+
+DECODER_4x16 d(half, I[3:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 16; i = i + 1) begin : d5_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 16], I[4], half[i]);
+    end
+endgenerate
 
 endmodule
 
@@ -117,7 +150,19 @@ output [15:0] D;
 // input
 input [3:0] I;
 
-// TBD
+wire [7:0] half;
+wire I_not;
+not I_inv(I_not, I[3]);
+
+DECODER_3x8 d(half, I[2:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 8; i = i + 1) begin : d4_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 8], I[3], half[i]);
+    end
+endgenerate
 
 
 endmodule
@@ -129,8 +174,19 @@ output [7:0] D;
 // input
 input [2:0] I;
 
-//TBD
+wire [3:0] half;
+wire I_not;
+not I_inv(I_not, I[2]);
 
+DECODER_2x4 d(half, I[1:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 4; i = i + 1) begin : d3_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 4], I[2], half[i]);
+    end
+endgenerate
 
 endmodule
 
@@ -141,6 +197,12 @@ output [3:0] D;
 // input
 input [1:0] I;
 
-// TBD
+wire I_not [1:0];
+not I_inv[1:0] (I_not, I);
+
+and (D[0], I_not[1], I_not[0]);
+and (D[1], I_not[1], I[0]);
+and (D[2], I[1], I_not[0]);
+and (D[3], I[1], I[0]);
 
 endmodule

mux.v

@@ -27,7 +27,16 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
 input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
 input [4:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
+                       I8, I9, I10, I11, I12, I13, I14, I15,
+                       S[3:0]
+);
+MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
+                       I24, I25, I26, I27, I28, I29, I30, I31,
+                       S[3:0]
+);
+MUX32_2x1 out(Y, x0, x1, S[4]);
 
 endmodule
 
@@ -55,7 +64,11 @@ input [31:0] I14;
 input [31:0] I15;
 input [3:0] S;
 
-// TBD
+
+wire [31:0] x0, x1;
+MUX32_8x1 mux8_0(x0, I0, I1, I2, I3, I4, I5, I6, I7, S[2:0]);
+MUX32_8x1 mux8_1(x1, I8, I9, I10, I11, I12, I13, I14, I15, S[2:0]);
+MUX32_2x1 out(Y, x0, x1, S[3]);
 
 endmodule
 
@@ -74,7 +87,10 @@ input [31:0] I6;
 input [31:0] I7;
 input [2:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_4x1 mux4_0(x0, I0, I1, I2, I3, S[1:0]);
+MUX32_4x1 mux4_1(x1, I4, I5, I6, I7, S[1:0]);
+MUX32_2x1 out(Y, x0, x1, S[2]);
 
 endmodule
 
@@ -89,7 +105,10 @@ input [31:0] I2;
 input [31:0] I3;
 input [1:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_2x1 mux2_0(x0, I0, I1, S[0]);
+MUX32_2x1 mux2_1(x1, I2, I3, S[0]);
+MUX32_2x1 out(Y, x0, x1, S[1]);
 
 endmodule
 
@@ -103,17 +122,19 @@ input [31:0] I1;
 input S;
 
 // only need 1 not gate
+wire S_not;
 not (S_not, S);
 
-wire [31:0] x0, x1;
+// wire [31:0] x0, x1;
 
 genvar i;
 generate
     for (i = 0; i < 32; i = i + 1)
     begin : mux32_gen_loop
-        and (x0[i], S_not, I0[i]);
-        and (x1[i], S, I1[i]);
-        or (Y[i], x0[i], x1[i]);
+        wire x0, x1;
+        and (x0, S_not, I0[i]);
+        and (x1, S, I1[i]);
+        or (Y[i], x0, x1);
     end
 endgenerate
 
@@ -126,6 +147,7 @@ output Y;
 //input list
 input I0, I1, S;
 
+wire S_not, x0, x1;
 not (S_not, S);
 and (x0, S_not, I0);
 and (x1, S, I1);

register_file.v

@@ -41,6 +41,27 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// TBD
+wire [31:0] Q [31:0];
+wire [31:0] r_write;
+DECODER_5x32 d_write(r_write, ADDR_W);
+
+REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
+
+wire [31:0] r1, r2;
+MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R1
+);
+MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R2
+);
+
+MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
+MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
 
 endmodule