lab-08: fix HiZ on register file when READ=0

Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32

Additional tests added in register file testbench.

TESTBENCH/register_file_tb.v

@@ -114,7 +114,6 @@ no_of_pass  = no_of_pass + 1;
 result[ridx] = DATA_R1; ridx=ridx+1;
 
 // TODO: Read and write from the same address at the same time?
-// TODO: Write when WRITE=0 should be tested
 
 #5    READ=1'b0; WRITE=1'b0; // No op
 

register_file.v

@@ -42,11 +42,8 @@ output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
 wire [31:0] Q [31:0];
-wire [31:0] r_write_sel, r_write;
+wire [31:0] r_write;
-DECODER_5x32 d_write(r_write_sel, ADDR_W);
+DECODER_5x32 d_write(r_write, ADDR_W);
-
-// only write when WRITE=1
-and write_active [31:0] (r_write, r_write_sel, WRITE);
 
 REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);