lab-08: gate level model for 32x32-bit register file

Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32

Additional tests added in register file testbench.

register_file.v

@@ -50,27 +50,22 @@ output [`DATA_INDEX_LIMIT:0] DATA_R2;
                      // I24, I25, I26, I27, I28, I29, I30, I31, S);
 
 wire [31:0] Q [31:0];
-wire [31:0] r_write;
-DECODER_5x32 d_write(r_write, ADDR_W);
+wire [31:0] write;
+DECODER_5x32 d_write(write, ADDR_W);
 
-REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
+REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
 
-wire [31:0] r1, r2;
-MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R1
 );
-MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R2
 );
 
-// TODO: Figure out this high Z thing and add a test for it.
-MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
-MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
-
 endmodule