Yuri Tatishchev
3091103f81
Gate level implementation for the following components: - SR_LATCH - D_LATCH - D_FF - REG1 - REG32
72 lines
2.8 KiB
Verilog
72 lines
2.8 KiB
Verilog
// Name: register_file.v
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// Module: REGISTER_FILE_32x32
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// Input: DATA_W : Data to be written at address ADDR_W
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// ADDR_W : Address of the memory location to be written
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// ADDR_R1 : Address of the memory location to be read for DATA_R1
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// ADDR_R2 : Address of the memory location to be read for DATA_R2
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// READ : Read signal
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// WRITE : Write signal
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// CLK : Clock signal
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// RST : Reset signal
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// Output: DATA_R1 : Data at ADDR_R1 address
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// DATA_R2 : Data at ADDR_R1 address
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//
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// Notes: - 32 bit word accessible dual read register file having 32 regsisters.
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// - Reset is done at -ve edge of the RST signal
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// - Rest of the operation is done at the +ve edge of the CLK signal
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// - Read operation is done if READ=1 and WRITE=0
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// - Write operation is done if WRITE=1 and READ=0
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// - X is the value at DATA_R* if both READ and WRITE are 0 or 1
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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// This is going to be +ve edge clock triggered register file.
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// Reset on RST=0
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module REGISTER_FILE_32x32(DATA_R1, DATA_R2, ADDR_R1, ADDR_R2,
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DATA_W, ADDR_W, READ, WRITE, CLK, RST);
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// input list
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input READ, WRITE, CLK, RST;
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input [`DATA_INDEX_LIMIT:0] DATA_W;
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input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
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// output list
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output [`DATA_INDEX_LIMIT:0] DATA_R1;
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output [`DATA_INDEX_LIMIT:0] DATA_R2;
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// module REG32(Q, D, LOAD, CLK, RESET);
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// module DECODER_5x32(D,I);
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// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
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// I8, I9, I10, I11, I12, I13, I14, I15,
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// I16, I17, I18, I19, I20, I21, I22, I23,
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// I24, I25, I26, I27, I28, I29, I30, I31, S);
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wire [31:0] Q [31:0];
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wire [31:0] write;
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DECODER_5x32 d_write(write, ADDR_W);
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REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
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MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
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Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
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Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
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Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
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ADDR_R1
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);
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MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
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Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
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Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
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Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
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ADDR_R2
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);
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endmodule
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