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f4a3e3bb8b
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lab-03: clean up twos complement modules
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2024-10-03 21:14:33 -07:00 |
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f5b19ae9fc
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lab-02: fix behavioral xor statement in RC_ADD_SUB modules
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2024-10-03 20:25:36 -07:00 |
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48bdad0e8b
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lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement
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2024-10-03 20:21:30 -07:00 |
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bb7e172316
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implement a Verilog gate level model for 64-bit Ripple Carry Adder and 32/64-bit twos complement
Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
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2024-10-02 16:18:00 -07:00 |
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3801d523de
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implement a Verilog gate level model for ripple carry adder subtractor
Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
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2024-10-01 20:42:02 -07:00 |
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d1475b5a4f
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implement a Verilog gate level model for ripple carry adder subtractor
Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
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2024-10-01 11:01:17 -07:00 |
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87e48f162e
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implement a Verilog gate level model for 32-bit basic logic gates
Gate level implementation for the following components:
- NOR32_2x1
- AND32_2x1
- INV32_1x1
- OR32_2x1
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2024-10-01 10:44:45 -07:00 |
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5520d6d716
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initial commit
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2024-10-01 10:39:56 -07:00 |
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