100 lines
2.9 KiB
Verilog
100 lines
2.9 KiB
Verilog
// Name: memory.v
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// Module: MEMORY_64MB
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// Input: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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// READ : Read signal
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// WRITE: Write signal
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// CLK : Clock signal
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// RST : Reset signal
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// Output: DATA : Data read out in the read operation
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//
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// Notes: - 32 bit word accessible 64MB memory.
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// - Reset is done at -ve edge of the RST signal
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// - Rest of the operation is done at the +ve edge of the CLK signal
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// - Read operation is done if READ=1 and WRITE=0
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// - Write operation is done if WRITE=1 and READ=0
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// - X is the value at DATA if both READ and WRITE are 0 or 1
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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module MEMORY_WRAPPER(DATA_OUT, DATA_IN, READ, WRITE, ADDR, CLK, RST);
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// parameter file
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// Parameter for the memory initialization file name
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parameter mem_init_file = "mem_content_01.dat";
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// output list
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output [`DATA_INDEX_LIMIT:0] DATA_OUT;
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//input list
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input [`DATA_INDEX_LIMIT:0] DATA_IN;
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input READ, WRITE, CLK, RST;
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input [`ADDRESS_INDEX_LIMIT:0] ADDR;
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reg [`DATA_INDEX_LIMIT:0] DATA_OUT;
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wire [`DATA_INDEX_LIMIT:0] DATA;
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assign DATA = ((READ===1'b0)&&(WRITE===1'b1))?DATA_IN:{`DATA_WIDTH{1'bz} };
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defparam memory_inst.mem_init_file = mem_init_file;
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MEMORY_64MB memory_inst(.DATA(DATA), .READ(READ), .WRITE(WRITE),
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.ADDR(ADDR), .CLK(CLK), .RST(RST));
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initial
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begin
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DATA_OUT = 32'h00000000;
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end
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always @(negedge RST)
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begin
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if (RST === 1'b0)
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DATA_OUT = 32'h00000000;
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end
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always @(DATA)
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begin
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if ((READ===1'b1)&&(WRITE===1'b0))
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DATA_OUT=DATA;
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end
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endmodule
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module MEMORY_64MB(DATA, READ, WRITE, ADDR, CLK, RST);
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// Parameter for the memory initialization file name
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parameter mem_init_file = "mem_content_01.dat";
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// input ports
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input READ, WRITE, CLK, RST;
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input [`ADDRESS_INDEX_LIMIT:0] ADDR;
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// inout ports
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inout [`DATA_INDEX_LIMIT:0] DATA;
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// memory bank
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reg [`DATA_INDEX_LIMIT:0] sram_32x64m [0:`MEM_INDEX_LIMIT]; // memory storage
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integer i; // index for reset operation
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reg [`DATA_INDEX_LIMIT:0] data_ret; // return data register
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assign DATA = ((READ===1'b1)&&(WRITE===1'b0))?data_ret:{`DATA_WIDTH{1'bz} };
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always @ (negedge RST or posedge CLK)
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begin
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if (RST === 1'b0)
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begin
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for(i=0;i<=`MEM_INDEX_LIMIT; i = i +1)
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sram_32x64m[i] = { `DATA_WIDTH{1'b0} };
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$readmemh(mem_init_file, sram_32x64m);
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end
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else
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begin
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if ((READ===1'b1)&&(WRITE===1'b0)) // read operation
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data_ret = sram_32x64m[ADDR];
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else if ((READ===1'b0)&&(WRITE===1'b1)) // write operation
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sram_32x64m[ADDR] = DATA;
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end
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end
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endmodule
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