project: add da vinci test programs

Gate level implementation for the following components:
- DECODER_5x32
- MUX32_32x1
- REGISTER_FILE_32x32

Additional tests added in register file testbench.

.gitignore

@@ -27,3 +27,7 @@ sc_dpiheader.h
 vsim.dbg
 
 # End of https://www.toptal.com/developers/gitignore/api/modelsim
+
+!TESTPROGRAM/*.dat
+!GOLDEN/*.dat
+!OUTPUT/*.dat

GOLDEN/CS147_FL15_HW01_02_mem_dump_golden.dat

@@ -0,0 +1,13 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000020
+00000020
+00000010
+00000010
+00000009
+00000008
+00000008
+00000005
+00000004
+00000002

GOLDEN/CS147_SP15_HW01_02_mem_dump_01_golden.dat

@@ -0,0 +1,9 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000001
+00000004
+00000004
+00000010
+00000010
+00000000

GOLDEN/CS147_SP15_HW01_02_mem_dump_02_golden.dat

@@ -0,0 +1,9 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000020
+00000008
+00000008
+00000002
+00000002

GOLDEN/CS147_SP17_HW01_02_mem_dump_golden.dat

@@ -0,0 +1,14 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000015
+00000017
+00000019
+0000001b
+0000001d
+0000001f
+00000021
+00000023
+00000025
+00000025
+00000000

GOLDEN/RevFib_mem_dump.golden.dat

@@ -0,0 +1,19 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+ffffffc9
+00000022
+ffffffeb
+0000000d
+fffffff8
+00000005
+fffffffd
+00000002
+ffffffff
+00000001
+00000000
+00000001
+00000001
+00000002
+00000003
+00000005

GOLDEN/fibonacci_mem_dump.golden.dat

@@ -0,0 +1,19 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000001
+00000001
+00000002
+00000003
+00000005
+00000008
+0000000d
+00000015
+00000022
+00000037
+00000059
+00000090
+000000e9
+00000179
+00000262

OUTPUT/CS147_FL15_HW01_02_mem_dump.dat

@@ -0,0 +1,13 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000

OUTPUT/CS147_SP17_HW01_02_mem_dump.dat

@@ -0,0 +1,14 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+0000000a
+0000000b
+0000000c
+0000000d
+0000000e
+0000000f
+00000010
+00000011
+00000012
+00000013
+00000000

OUTPUT/RevFib_mem_dump.dat

@@ -0,0 +1,19 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000

OUTPUT/fibonacci_mem_dump.dat

@@ -0,0 +1,19 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000

OUTPUT/full_adder.out

@@ -0,0 +1,11 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/FULL_ADDER_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000001
+00000001
+00000002
+00000001
+00000002
+00000002
+00000003

OUTPUT/half_adder.out

@@ -0,0 +1,7 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/HALF_ADDER_TB/results
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000
+00000001
+00000001
+00000002

OUTPUT/mult32_tb.out

@@ -0,0 +1,11 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/MULT_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000000000c8
+000000000000002d
+ffffffffffffff90
+ffffffffffffff42
+3100000000000000
+cf00000000000000
+cf00000000000000
+3100000000000000

OUTPUT/mult32_u_tb.out

@@ -0,0 +1,8 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/MULT_U_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+00000000000000c8
+000000000000002d
+0000000000000070
+00000000000000be
+006975a0b62bf524

OUTPUT/rc_add_sub_32.out

@@ -0,0 +1,8 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/RC_ADD_SUB_32_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+0000001e
+fffffff6
+00000003
+00000004
+00005555

OUTPUT/twoscomp32_tb.out

@@ -0,0 +1,5 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/TWOSCOMP32_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+fffffff6
+00000005

OUTPUT/twoscomp64_tb.out

@@ -0,0 +1,5 @@
+// memory data file (do not edit the following line - required for mem load use)
+// instance=/TWOSCOMP64_TB/result
+// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
+fffffffffffffff6
+0000000000000005

TESTBENCH/register_file_tb.v

@@ -68,24 +68,53 @@ no_of_pass = 0;
 // Write cycle
 for(i=0;i<32; i = i + 1)
 begin
-#10     DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
+#10     DATA_REG = i * 10; READ=1'b0; WRITE=1'b1; ADDR_W = i;
 end
 
 #5 READ=1'b0; WRITE=1'b0;
 // test of write data
 for(i=0;i<32; i = i + 1)
 begin
-#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
+#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i % 7;
 #5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== i)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
+        if (DATA_R1 !== i * 10)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 10, DATA_R1);
+        else if (DATA_R2 !== (i % 7) * 10)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, (i % 7) * 10, DATA_R2);
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
+// Testing read and write at the same time
+for(i=2;i<16; i = i + 1)
+begin
+#5      DATA_REG = 20; READ=1'b1; WRITE=1'b1; ADDR_W = i + 1; ADDR_R1 = i; ADDR_R2 = i * 2;
+#5      no_of_test = no_of_test + 1;
+        if (DATA_R1 !== 20)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, 20, DATA_R1);
+        else if (DATA_R2 !== i * 20)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 20, DATA_R2);
+        else
+	    no_of_pass  = no_of_pass + 1;
+        result[ridx] = DATA_R1; ridx=ridx+1;
+
+end
+
+// Test reading when READ=0
+#5     READ=1'b0;
+#5     no_of_test = no_of_test + 1;
+if (DATA_R1 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
+else if (DATA_R2 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
+else
+no_of_pass  = no_of_pass + 1;
+result[ridx] = DATA_R1; ridx=ridx+1;
+
+// TODO: Read and write from the same address at the same time?
+// TODO: Write when WRITE=0 should be tested
 
 #5    READ=1'b0; WRITE=1'b0; // No op
 

TESTPROGRAM/CS147_FL15_HW01_02.dat

@@ -0,0 +1,45 @@
+// ------ Program Part ----
+@0001000
+2021000A 	//		addi r1, r1, 0xA;
+20421008 	// 		addi r2, r2, 0x1008;
+00401301	// 		sll r2, r2, 0xC;
+00411820 	// 		add r3, r2, r1;
+3C848000 	// 		lui r4, r4, 0x8000;
+8C450000 	// LOOP: 	lw r5, r2,0x0;
+8C660000 	// 		lw r6, r3, 0x0;
+00A63822 	// 		sub r7, r5, r6;
+00E44024 	// 		and r8, r7, r4;
+15280003	// 		bne r8, r9, L1;
+20C00000	// 		addi r0, r6, 0x0;
+20630001	// 		addi r3, r3, 0x1;
+0800100F	// 		jmp L2;
+20A00000	// L1: 	addi r0, r5, 0x0;
+20420001	// 		addi r2, r2, 0x1;
+6C000000	// L2: 	push
+2021FFFF	// 		addi r1, r1, 0xFFFF;
+1521FFF3	// 		bne r1, r9, LOOP;
+
+
+// ------ Data Part ----
+@01008000
+005 	// 01008000
+008	// 01008001
+009	// 01008002 
+010	// 01008003
+020	// 01008004
+029	// 01008005
+02D	// 01008006
+02F	// 01008007 
+032	// 01008008
+037	// 01008009 
+002	// 0100800A
+004	// 0100800B
+008	// 0100800C
+010	// 0100800D
+020	// 0100800E 
+040	// 0100800F
+080	// 01008010 
+100	// 01008011 
+200	// 01008012 
+400	// 01008013
+

TESTPROGRAM/CS147_SP15_HW01_02.dat

@@ -0,0 +1,21 @@
+@0001000
+20000001 	// 		addi r0, r0, 0x1;
+20210002 	//		addi r1, r1, 0x2;
+20420000 	//		addi r2, r2, 0x0;
+3C630100 	//		lui r3, 0x100;
+34638000 	//		ori r3, r3, 0x8000;
+20840005 	//		addi r4, r4, 0x5;
+00010020 	// LOOP: 	add r0, r0, r1;
+00010822 	//		sub r1, r0, r1;
+00010022 	//		sub r0, r0, r1;
+AC610000 	//		sw r1, r3, 0x0;
+20630001	//		addi r3, r3, 0x1;
+6C000000	//		push;
+00000041	//		sll r0, r0, 0x1;
+00200841	//		sll r1, r1, 0x1;
+20420001	//		addi r2, r2, 0x1;
+1482FFF6	//		bne r2, r4, LOOP;
+
+
+
+

TESTPROGRAM/CS147_SP17_HW01_02.dat

@@ -0,0 +1,28 @@
+// ------ Program Part ----
+@0001000
+20001008 	// 		addi r0, r0, 0x1008
+00000301 	// 		sll r0, r0, 0xC
+20420009	// 		addi r2, r2, 0x9
+10410007 	// LOOP: 	beq r1, r2, END
+8C030000 	//		lw r3, r0, 0x0
+8C040001	//		lw r4, r0, 0x1
+00642820 	//		add r5, r3, r4
+AC050000 	//		sw r5, r0, 0x0
+20000001 	//		addi r0, r0, 0x1
+20210001	//		addi r1, r1, 0x1
+08001003	//		j LOOP
+AC050000	// END: 	sw r5, r0, 0x0
+
+// ------ Data Part ----
+@01008000
+0A	// 0100 8000
+0B	// 0100 8001
+0C	// 0100 8002
+0D	// 0100 8003
+0E	// 0100 8004
+0F	// 0100 8005
+10	// 0100 8006
+11	// 0100 8007
+12	// 0100 8008
+13	// 0100 8008
+

TESTPROGRAM/RevFib.dat

@@ -0,0 +1,16 @@
+@0001000
+20210005 //        addi r1, r1, 0x5
+20420003 //        addi r2, r2, 0x3
+20200000 //        addi r0, r1, 0x0 
+6c000000 //        push
+20400000 // loop : addi r0, r2, 0x0
+6c000000 //        push
+20430000 //        addi r3, r2, 0x0
+00221022 //        sub  r2, r1, r2
+20610000 //        addi r1, r3, 0x0
+08001004 //        jmp loop
+00000000 //        nop
+00000000 //        nop
+
+
+

TESTPROGRAM/fibonacci.dat

@@ -0,0 +1,13 @@
+@0001000
+20420001 //         addi r2, r2, 0x0001;
+3C000100 //         lui  r0, 0x0100;
+AC010000 //         sw   r1, r0, 0x0000;
+20000001 // loop:   addi r0, r0, 0x0001;
+AC020000 //         sw   r2, r0, 0x0000;
+20430000 //         addi r3, r2, 0x0000;
+00411020 //         add  r2, r2, r1;
+20610000 //         addi r1, r3, 0x0000;
+08001003 //         jmp  loop;
+
+
+

TESTPROGRAM/mem_content_01.dat

@@ -0,0 +1,11 @@
+@0001000
+00414020 00414021 00414022 00414023 // sample data
+00414024 00414025 00414026 00414027 
+00414028 00414029 0041402a 0041402b 
+0041402c 0041402d 0041402e 0041402f 
+
+@002f00a
+00514020 00514021 00514022 00514023 
+00514024 00514025 00514026 00514027 
+00514028 00514029 0051402a 0051402b 
+0051402c 0051402d 0051402e 0051402f 

alu.v

@@ -44,7 +44,7 @@ wire [31:0] res,
 // can use oprn[1] or oprn[3] for SnA
 wire SnA;
 or (SnA, OPRN[1], OPRN[3]);
-RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
+RC_ADD_SUB_32 addsub(.Y(res_addsub), .CO(), .A(OP1), .B(OP2), .SnA(SnA));
 buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
 
 // shift_r = xx0100
@@ -54,7 +54,7 @@ buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
 SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
 
 // mul = xx0011
-MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
+MULT32 mul(.LO(res_mul), .HI(), .A(OP1), .B(OP2));
 
 // and = xx0110
 // or  = xx0111
@@ -63,11 +63,12 @@ AND32_2x1 and32(res_and, OP1, OP2);
 OR32_2x1 or32(res_or, OP1, OP2);
 NOR32_2x1 nor32(res_nor, OP1, OP2);
 
-MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
+MUX32_16x1 out(.Y(res), .S(OPRN[3:0]), .I0(),
                .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
                .I4(res_shift),.I5(res_shift),
                .I6(res_and), .I7(res_or), .I8(res_nor),
-               .I9(res_slt)
+               .I9(res_slt),
+               .I10(), .I11(), .I12(), .I13(), .I14(), .I15()
 );
 
 // or bits of result for zero flag

control_unit.v

@@ -27,7 +27,314 @@ output READ, WRITE;
 input ZERO, CLK, RST;
 input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
 
+task print_instruction;
+input  [`DATA_INDEX_LIMIT:0] inst;
+reg [5:0]   opcode2;
+reg [4:0]   rs2;
+reg [4:0]   rt2;
+reg [4:0]   rd2;
+reg [4:0]   shamt2;
+reg [5:0]   funct2;
+reg [15:0]  immediate2;
+reg [25:0]  address2;
+begin
+// parse the instruction
+// R-type
+{opcode2, rs2, rt2, rd2, shamt2, funct2} = inst;
+// I-type
+{opcode2, rs2, rt2, immediate2 } = inst;
+// J-type
+{opcode2, address2} = inst;
+
+$write("@ %6dns -> [0X%08h] ", $time, inst);
+
+case(opcode2)
+// R-Type
+6'h00 : begin
+            case(funct2)
+                6'h20: $write("add  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h22: $write("sub  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h2c: $write("mul  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h24: $write("and  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+ 		6'h25: $write("or   r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h27: $write("nor  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h2a: $write("slt  r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
+                6'h01: $write("sll  r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
+                6'h02: $write("srl  r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
+                6'h08: $write("jr   r[%02d];", rs2);
+                default: begin $write("");
+		end
+            endcase
+        end
+// I-type
+6'h08 : $write("addi  r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h1d : $write("muli  r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h0c : $write("andi  r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h0d : $write("ori   r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h0f : $write("lui   r[%02d], 0X%04h;", rt2, immediate2);
+6'h0a : $write("slti  r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h04 : $write("beq   r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h05 : $write("bne   r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h23 : $write("lw    r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+6'h2b : $write("sw    r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
+// J-Type
+6'h02 : $write("jmp   0X%07h;", address2);
+6'h03 : $write("jal   0X%07h;", address2);
+6'h1b : $write("push;");
+6'h1c : $write("pop;");
+default: $write("");
+endcase
+
+$write("\n");
+end
+endtask
+//------------------------------------- END ---------------------------------------//
+
+
+reg read, write;
+assign READ = read;
+assign WRITE = write;
+
+// Control signals, same as in data_path.v
+reg pc_load, pc_sel_1, pc_sel_2, pc_sel_3,
+    ir_load, reg_r, reg_w,
+    r1_sel_1, wa_sel_1, wa_sel_2, wa_sel_3,
+
+    sp_load, op1_sel_1,
+    op2_sel_1, op2_sel_2, op2_sel_3, op2_sel_4,
+
+    wd_sel_1, wd_sel_2, wd_sel_3,
+    ma_sel_1, ma_sel_2,
+    md_sel_1;
+
+reg [5:0] alu_oprn;
+
+buf (CTRL[0], pc_load);
+buf (CTRL[1], pc_sel_1);
+buf (CTRL[2], pc_sel_2);
+buf (CTRL[3], pc_sel_3);
+
+buf (CTRL[4], ir_load);
+buf (CTRL[5], reg_r);
+buf (CTRL[6], reg_w);
+
+buf (CTRL[7], r1_sel_1);
+buf (CTRL[8], wa_sel_1);
+buf (CTRL[9], wa_sel_2);
+buf (CTRL[10], wa_sel_3);
+
+buf (CTRL[11], sp_load);
+buf (CTRL[12], op1_sel_1);
+
+buf (CTRL[13], op2_sel_1);
+buf (CTRL[14], op2_sel_2);
+buf (CTRL[15], op2_sel_3);
+buf (CTRL[16], op2_sel_4);
+
+buf (CTRL[17], wd_sel_1);
+buf (CTRL[18], wd_sel_2);
+buf (CTRL[19], wd_sel_3);
+
+buf (CTRL[20], ma_sel_1);
+buf (CTRL[21], ma_sel_2);
+
+buf (CTRL[22], md_sel_1);
+
+buf alu_oprn_buf [5:0] (CTRL[28:23], alu_oprn);
+
+// Parse the instruction data, same as in data_path.v
+wire [5:0]   opcode;
+wire [4:0]   rs;
+wire [4:0]   rt;
+wire [4:0]   rd;
+wire [4:0]   shamt;
+wire [5:0]   funct;
+wire [15:0]  imm;
+wire [25:0]  addr;
+
+// common for all
+buf opcode_buf [5:0] (opcode, INSTRUCTION[31:26]);
+// common for R-type, I-type
+buf rs_buf [4:0] (rs, INSTRUCTION[25:21]);
+buf rt_buf [4:0] (rt, INSTRUCTION[20:16]);
+// for R-type
+buf rd_buf [4:0] (rd, INSTRUCTION[15:11]);
+buf shamt_buf [4:0] (shamt, INSTRUCTION[10:6]);
+buf funct_buf [5:0] (funct, INSTRUCTION[5:0]);
+// for I-type
+buf imm_buf [15:0] (imm, INSTRUCTION[15:0]);
+// for J-type
+buf addr_buf [25:0] (addr, INSTRUCTION[25:0]);
+
+// State machine
+wire [2:0] state;
+PROC_SM proc_sm(state, CLK, RST);
+
 // TBD - take action on each +ve edge of clock
+always @ (state) begin
+    // Print current state
+    $write("@ %6dns -> ", $time);
+    $write("STATE ", state, ": ");
+    case (state)
+        `PROC_FETCH: $write("FETCH");
+        `PROC_DECODE: $write("DECODE");
+        `PROC_EXE: $write("EXECUTE");
+        `PROC_MEM: $write("MEMORY");
+        `PROC_WB: $write("WRITE BACK");
+        default: $write("INVALID");
+    endcase
+
+    case (state)
+        // fetch - next instruction from memory at PC
+        `PROC_FETCH: begin
+            // loaded in previous state, set to 0
+            pc_load = 1'b0;
+            reg_r = 1'b0;
+            reg_w = 1'b0;
+            // load now
+            ir_load = 1'b1;
+            read = 1'b1;
+            write = 1'b0;
+            // selections
+            // ma_sel_2 - load data from mem[PC]
+            ma_sel_2 = 1'b1;
+        end
+        // decode - parse instruction and read values from register file
+        `PROC_DECODE: begin
+            // loaded in previous state, set to 0
+            ir_load = 1'b0;
+            sp_load = 1'b0;
+            read = 1'b0;
+            // load now
+            reg_r = 1'b1;
+            reg_w = 1'b0;
+            // selections
+            // r1_sel_1: push - store value of r0 at stack pointer
+            r1_sel_1 = opcode != 6'h1b ? 1'b0 : 1'b1;
+            // wa_sel_1: R-type - write to rd, I-type - write to rt
+            wa_sel_1 = opcode == 6'h00 ? 1'b0 : 1'b1;
+            // wa_sel_2: jal - write to r31, pop - write to r0
+            wa_sel_2 = opcode == 6'h03 ? 1'b1 : 1'b0;
+            // wa_sel_3: push or pop - wa_sel_2, else wa_sel_1
+            wa_sel_3 = opcode == 6'h03 || opcode == 6'h1c ? 1'b0 : 1'b1;
+            // jr - jump to address in register
+            pc_sel_1 = opcode == 6'h00 && funct == 6'h08 ? 1'b0 : 1'b1;
+            // beq, bne - branch if equal or not equal
+            // TODO: this should only be selected if the condition is met
+            // pc_sel_2 = opcode == 6'h04 || opcode == 6'h05 ? 1'b1 : 1'b0;
+            // jmp, jal - jump to address
+            pc_sel_3 = opcode == 6'h02 || opcode == 6'h03 ? 1'b0 : 1'b1;
+
+            // alu_oprn - operation to be performed by ALU
+            // R-type
+            if (opcode == 6'h00) begin
+                case (funct)
+                    6'h20: alu_oprn = 6'h01; // add
+                    6'h22: alu_oprn = 6'h02; // sub
+                    6'h2c: alu_oprn = 6'h03; // mul
+                    6'h02: alu_oprn = 6'h04; // srl
+                    6'h01: alu_oprn = 6'h05; // sll
+                    6'h24: alu_oprn = 6'h06; // and
+                    6'h25: alu_oprn = 6'h07; // or
+                    6'h27: alu_oprn = 6'h08; // nor
+                    6'h2a: alu_oprn = 6'h09; // slt
+                    default: alu_oprn = 6'hxx;
+                endcase
+            end
+            // I-type and J-type
+            else begin
+                case (opcode)
+                    // I-type
+                    6'h08: alu_oprn = 6'h01; // addi
+                    6'h1d: alu_oprn = 6'h03; // muli
+                    6'h0c: alu_oprn = 6'h06; // andi
+                    6'h0d: alu_oprn = 6'h07; // ori
+                    6'h0a: alu_oprn = 6'h09; // slti
+                    6'h04: alu_oprn = 6'h02; // beq - sub
+                    6'h05: alu_oprn = 6'h02; // bne - sub
+                    6'h23: alu_oprn = 6'h01; // lw - add
+                    6'h2b: alu_oprn = 6'h01; // sw - add
+                    // J-type
+                    6'h1b: alu_oprn = 6'h02; // push - sub
+                    6'h1c: alu_oprn = 6'h01; // pop - add
+                    default: alu_oprn = 6'hxx;
+                endcase
+            end
+            // op1_sel_1 - select r1 or sp based on opcode
+            // push or pop - sp, else r1
+            op1_sel_1 = opcode == 6'h1b || opcode == 6'h1c ? 1'b1 : 1'b0;
+            // op2_sel_1 - select 1 or shamt based on alu_oprn
+            // sll or srl - shamt, else 1 (for increments/decrements)
+            op2_sel_1 = alu_oprn == 6'h04 || alu_oprn == 6'h05 ? 1'b1 : 1'b0;
+            // op2_sel_2 - select imm_zx or imm_sx based on alu_oprn
+            // logical (and, or) - imm_zx, else imm_sx; ('nor' not availble in I-type)
+            op2_sel_2 = alu_oprn == 6'h06 || alu_oprn == 6'h07 ? 1'b0 : 1'b1;
+            // op2_sel_3 - select op2_sel_2 or op2_sel_1 based on alu_oprn
+            // R-type - op2_sel_1, I-type - op2_sel_2
+            op2_sel_3 = opcode == 6'h00 ? 1'b1 : 1'b0;
+            // op2_sel_4 - select op2_sel_3 or r2
+            // I-type or shift or inc/dec - op2_sel_3, else r2
+            // i.e. r2 only if R-type and not shift
+            op2_sel_4 = opcode != 6'h00 || alu_oprn == 6'h04 || alu_oprn == 6'h05 ? 1'b0 : 1'b1;
+        end
+        // execute - perform operation based on instruction
+        `PROC_EXE: begin
+            // selections
+            // wd_sel_1 - alu_out or DATA_IN
+            wd_sel_1 = 1'b0;
+            // wd_sel_2 - wd_sel_1 or imm_zx_lsb
+            // lui - imm_zx_lsb, else wd_sel_1
+            wd_sel_2 = opcode == 6'h0f ? 1'b1 : 1'b0;
+            // wd_sel_3 - pc_inc or wd_sel_2
+            // jal - pc_inc, else wd_sel_2
+            wd_sel_3 = opcode == 6'h03 ? 1'b0 : 1'b1;
+            // md_sel_1 - r1 for push, r2 for sw
+            md_sel_1 = opcode == 6'h1b ? 1'b1 : 1'b0;
+        end
+        `PROC_MEM: begin
+            // load now
+            // push or sw - write to memory
+            if (opcode == 6'h1b || opcode == 6'h2b) begin
+                read = 1'b0;
+                write = 1'b1;
+            end
+            else begin
+                read = 1'b1;
+                write = 1'b0;
+            end
+        end
+        `PROC_WB: begin
+            // loaded in previous state, set to 0
+            read = 1'b0;
+            write = 1'b0;
+            // load now
+            pc_load = 1'b1;
+            // write to register file if
+            // R-type (except jr) or I-type (except beq, bne, sw) or pop or jal
+            reg_w = (opcode == 6'h00 && funct != 6'h08) // R-type (except jr)
+                    || (opcode == 6'h08 || opcode == 6'h1d || opcode == 6'h0c || opcode == 6'h0d
+                    || opcode == 6'h0f || opcode == 6'h0a || opcode == 6'h23) // I-type (except beq, bne, sw)
+                    || (opcode == 6'h1c || opcode == 6'h03) // pop or jal
+                    ? 1'b1 : 1'b0;
+            // selections
+            // ma_sel_2 - load data from mem[PC]
+            ma_sel_2 = 1'b1;
+            // pc_sel_2 - branch if equal or not equal
+            pc_sel_2 = (opcode == 6'h04 && ZERO) || (opcode == 6'h05 && ~ZERO) ? 1'b1 : 1'b0;
+
+        end
+        default: begin
+            $write("@ %6dns -> ", $time);
+            $write("STATE ", state, ": ");
+            $write("INVALID");
+            print_instruction(INSTRUCTION);
+        end
+    endcase
+
+    // TBD - assign control signals based on instruction
+    print_instruction(INSTRUCTION);
+    // TBD - assign READ and WRITE signals based on instruction
+end
 
 endmodule
 
@@ -56,6 +363,25 @@ input CLK, RST;
 // list of outputs
 output [2:0] STATE;
 
+reg [2:0] state_sel = 3'bxxx;
+
+always @ (negedge RST) begin
+    // set to invalid value, so that it defaults to fetch
+    state_sel = 3'bxxx;
+end
+
 // TBD - take action on each +ve edge of clock
+always @ (posedge CLK) begin
+    case (state_sel)
+        `PROC_FETCH: state_sel = `PROC_DECODE;
+        `PROC_DECODE: state_sel = `PROC_EXE;
+        `PROC_EXE: state_sel = `PROC_MEM;
+        `PROC_MEM: state_sel = `PROC_WB;
+        `PROC_WB: state_sel = `PROC_FETCH;
+        default: state_sel = `PROC_FETCH;
+    endcase
+end
+
+assign STATE = state_sel;
 
 endmodule

data_path.v

@@ -29,6 +29,149 @@ input [`CTRL_WIDTH_INDEX_LIMIT:0]  CTRL;
 input CLK, RST;
 input [`DATA_INDEX_LIMIT:0] DATA_IN;
 
-// TBD
+wire pc_load, pc_sel_1, pc_sel_2, pc_sel_3,
+    ir_load, reg_r, reg_w,
+    r1_sel_1, wa_sel_1, wa_sel_2, wa_sel_3,
+
+    sp_load, op1_sel_1,
+    op2_sel_1, op2_sel_2, op2_sel_3, op2_sel_4,
+
+    wd_sel_1, wd_sel_2, wd_sel_3,
+    ma_sel_1, ma_sel_2,
+    md_sel_1;
+
+wire [5:0] alu_oprn;
+
+buf (pc_load, CTRL[0]);
+buf (pc_sel_1, CTRL[1]);
+buf (pc_sel_2, CTRL[2]);
+buf (pc_sel_3, CTRL[3]);
+
+buf (ir_load, CTRL[4]);
+buf (reg_r, CTRL[5]);
+buf (reg_w, CTRL[6]);
+
+buf (r1_sel_1, CTRL[7]);
+buf (wa_sel_1, CTRL[8]);
+buf (wa_sel_2, CTRL[9]);
+buf (wa_sel_3, CTRL[10]);
+
+buf (sp_load, CTRL[11]);
+buf (op1_sel_1, CTRL[12]);
+
+buf (op2_sel_1, CTRL[13]);
+buf (op2_sel_2, CTRL[14]);
+buf (op2_sel_3, CTRL[15]);
+buf (op2_sel_4, CTRL[16]);
+
+buf (wd_sel_1, CTRL[17]);
+buf (wd_sel_2, CTRL[18]);
+buf (wd_sel_3, CTRL[19]);
+
+buf (ma_sel_1, CTRL[20]);
+buf (ma_sel_2, CTRL[21]);
+
+buf (md_sel_1, CTRL[22]);
+
+buf alu_oprn_buf [5:0] (alu_oprn, CTRL[28:23]);
+
+// variables
+wire [31:0] ir; // Instruction Register
+wire [31:0] r1, r2; // Register File
+wire [31:0] pc, pc_inc; // Program Counter
+wire [31:0] sp; // Stack Pointer
+wire [31:0] alu_out; // ALU output
+
+// TODO: Why?
+buf ir_buf [31:0] (INSTRUCTION, ir);
+
+// Parse the instruction data
+wire [5:0]   opcode;
+wire [4:0]   rs;
+wire [4:0]   rt;
+wire [4:0]   rd;
+wire [4:0]   shamt;
+wire [5:0]   funct;
+wire [15:0]  imm;
+wire [25:0]  addr;
+
+// common for all
+buf opcode_buf [5:0] (opcode, ir[31:26]);
+// common for R-type, I-type
+buf rs_buf [4:0] (rs, ir[25:21]);
+buf rt_buf [4:0] (rt, ir[20:16]);
+// for R-type
+buf rd_buf [4:0] (rd, ir[15:11]);
+buf shamt_buf [4:0] (shamt, ir[10:6]);
+buf funct_buf [5:0] (funct, ir[5:0]);
+// for I-type
+buf imm_buf [15:0] (imm, ir[15:0]);
+// for J-type
+buf addr_buf [25:0] (addr, ir[25:0]);
+
+
+// Instruction Register input
+// Instruction Register
+REG32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(ir_load), .CLK(CLK), .RESET(RST));
+
+// Register File Input
+wire [31:0] r1_sel, wa_sel, wd_sel;
+wire [31:0] wa_sel_p1, wa_sel_p2, wd_sel_p1, wd_sel_p2;
+wire [31:0] imm_zx_lsb;
+buf imm_zx_lsb_buf [31:0] (imm_zx_lsb, {imm, 16'b0});
+MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, r1_sel_1);
+MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, wa_sel_1);
+// TODO: Why 31?
+MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, wa_sel_2);
+MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, wa_sel_3);
+MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, wd_sel_1);
+MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, wd_sel_2);
+MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, wd_sel_3);
+// Register File
+REGISTER_FILE_32x32 rf_inst(.DATA_R1(r1), .DATA_R2(r2), .ADDR_R1(r1_sel[4:0]), .ADDR_R2(rt),
+                            .DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(reg_r), .WRITE(reg_w), .CLK(CLK), .RST(RST));
+
+// ALU Input
+wire [31:0] op1_sel, op2_sel;
+wire [31:0] op2_sel_p1, op2_sel_p2, op2_sel_p3;
+wire [31:0] shamt_zx, imm_sx, imm_zx;
+buf shamt_zx_buf [31:0] (shamt_zx, {27'b0, shamt});
+buf imm_sx_buf [31:0] (imm_sx, {{16{imm[15]}}, imm});
+buf imm_zx_buf [31:0] (imm_zx, {16'b0, imm});
+MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, op1_sel_1);
+MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, op2_sel_1);
+MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, op2_sel_2);
+MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, op2_sel_3);
+MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, op2_sel_4);
+// ALU
+ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(alu_oprn));
+
+// Progam Counter Input
+wire [31:0] pc_sel;
+wire [31:0] pc_offset, pc_jump, pc_sel_p1, pc_sel_p2;
+RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0));
+MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, pc_sel_1);
+RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_offset), .CO(), .A(pc), .B(imm_sx), .SnA(1'b0));
+MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_offset, pc_sel_2);
+buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr});
+MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, pc_sel_3);
+// Program Counter
+defparam pc_inst.PATTERN = `INST_START_ADDR;
+REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(pc_load), .CLK(CLK), .RESET(RST));
+
+// Stack Pointer
+defparam sp_inst.PATTERN = `INIT_STACK_POINTER;
+REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(sp_load), .CLK(CLK), .RESET(RST));
+
+// Data out
+MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, md_sel_1);
+
+// Address out
+wire [31:0] ma_sel_p1;
+MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, ma_sel_1);
+// TODO: Check address calculation since it's 26 bit
+(* keep="soft" *)
+wire [5:0] _addr_ignored;
+MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, ma_sel_2);
 
 endmodule

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -31,7 +31,31 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(), .A(0), .B(A), .SnA(1'b1));
+
+endmodule
+
+// 32-bit register with parameterized preset pattern
+module REG32_PP(Q, D, LOAD, CLK, RESET);
+parameter PATTERN = 32'h00000000;
+output [31:0] Q;
+
+input CLK, LOAD;
+input [31:0] D;
+input RESET;
+
+wire [31:0] qbar;
+
+genvar i;
+generate
+    for(i=0; i<32; i=i+1)
+    begin : reg32_gen_loop
+       if (PATTERN[i] == 0)
+              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(1'b1), .nR(RESET));
+        else
+              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(RESET), .nR(1'b1));
+    end
+endgenerate
 
 endmodule
 
@@ -127,7 +151,19 @@ output [31:0] D;
 // input
 input [4:0] I;
 
-// TBD
+wire [15:0] half;
+wire I_not;
+not I_inv(I_not, I[4]);
+
+DECODER_4x16 d(half, I[3:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 16; i = i + 1) begin : d5_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 16], I[4], half[i]);
+    end
+endgenerate
 
 endmodule
 
@@ -138,7 +174,19 @@ output [15:0] D;
 // input
 input [3:0] I;
 
-// TBD
+wire [7:0] half;
+wire I_not;
+not I_inv(I_not, I[3]);
+
+DECODER_3x8 d(half, I[2:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 8; i = i + 1) begin : d4_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 8], I[3], half[i]);
+    end
+endgenerate
 
 
 endmodule
@@ -150,8 +198,19 @@ output [7:0] D;
 // input
 input [2:0] I;
 
-//TBD
+wire [3:0] half;
+wire I_not;
+not I_inv(I_not, I[2]);
 
+DECODER_2x4 d(half, I[1:0]);
+
+genvar i;
+generate
+    for (i = 0; i < 4; i = i + 1) begin : d3_gen
+        and msb0(D[i], I_not, half[i]);
+        and msb1(D[i + 4], I[2], half[i]);
+    end
+endgenerate
 
 endmodule
 

mux.v

@@ -27,7 +27,16 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
 input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
 input [4:0] S;
 
-// TBD
+wire [31:0] x0, x1;
+MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
+                       I8, I9, I10, I11, I12, I13, I14, I15,
+                       S[3:0]
+);
+MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
+                       I24, I25, I26, I27, I28, I29, I30, I31,
+                       S[3:0]
+);
+MUX32_2x1 out(Y, x0, x1, S[4]);
 
 endmodule
 

register_file.v

@@ -41,6 +41,30 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// TBD
+wire [31:0] Q [31:0];
+wire [31:0] r_write_sel, r_write;
+DECODER_5x32 d_write(r_write_sel, ADDR_W);
+
+// only write when WRITE=1
+and write_active [31:0] (r_write, r_write_sel, WRITE);
+
+REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
+
+wire [31:0] r1, r2;
+MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R1
+);
+MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R2
+);
+
+MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
+MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
 
 endmodule