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7e4a63e155
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(WIP) lab-08: Decoder_5x32, Mux32_32x1
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2024-10-19 16:51:30 -07:00 |
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41ecb62082
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lab-07: gate level model for 32-bit register
Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32
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2024-10-19 16:05:17 -07:00 |
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a110f7c042
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(WIP): REG1
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2024-10-19 15:54:51 -07:00 |
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7c0645eaa1
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(WIP): D Latch and D FlipFlop
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2024-10-19 15:47:35 -07:00 |
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d217faf166
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(WIP): SR Latch
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2024-10-19 15:20:23 -07:00 |
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800b80ef85
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lab-06 (WIP): mux32_16x1 working
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2024-10-10 15:14:25 -07:00 |
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597e245641
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lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement
Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
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2024-10-03 21:30:23 -07:00 |
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5520d6d716
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initial commit
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2024-10-01 10:39:56 -07:00 |
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