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3091103f81
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lab-07: gate level model for 32-bit register
Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32
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2024-10-19 18:39:30 -07:00 |
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cce0c524d9
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lab-06: gate level model for Arithmetic & Logic Unit
Gate level implementation for the following components:
- ALU
- MUX32_16x1
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2024-10-19 18:39:23 -07:00 |
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1ab4ea027d
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lab-05: gate level model for 32-bit barrel shifter
Gate level implementation for the following components:
- SHIFT32_L
- SHIFT32_R
- BARREL_SHIFTER32
- SHIFT32
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2024-10-19 18:39:16 -07:00 |
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5a4b5a312a
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lab-04: gate level model for 32-bit signed multiplier
Gate level implementation for the following components:
- MULT32_U
- MULT32
- MUX32_2x1
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2024-10-19 18:39:02 -07:00 |
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5520d6d716
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initial commit
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2024-10-01 10:39:56 -07:00 |
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