Yuri Tatishchev
5a4b5a312a
Gate level implementation for the following components: - MULT32_U - MULT32 - MUX32_2x1
135 lines
2.5 KiB
Coq
135 lines
2.5 KiB
Coq
// Name: mux.v
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// Module:
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// Input:
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// Output:
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//
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// Notes: Common definitions
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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// 32-bit mux
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module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
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I8, I9, I10, I11, I12, I13, I14, I15,
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I16, I17, I18, I19, I20, I21, I22, I23,
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I24, I25, I26, I27, I28, I29, I30, I31, S);
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// output list
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output [31:0] Y;
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//input list
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input [31:0] I0, I1, I2, I3, I4, I5, I6, I7;
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input [31:0] I8, I9, I10, I11, I12, I13, I14, I15;
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input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
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input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
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input [4:0] S;
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// TBD
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endmodule
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// 32-bit 16x1 mux
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module MUX32_16x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
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I8, I9, I10, I11, I12, I13, I14, I15, S);
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// output list
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output [31:0] Y;
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//input list
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input [31:0] I0;
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input [31:0] I1;
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input [31:0] I2;
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input [31:0] I3;
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input [31:0] I4;
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input [31:0] I5;
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input [31:0] I6;
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input [31:0] I7;
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input [31:0] I8;
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input [31:0] I9;
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input [31:0] I10;
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input [31:0] I11;
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input [31:0] I12;
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input [31:0] I13;
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input [31:0] I14;
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input [31:0] I15;
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input [3:0] S;
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// TBD
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endmodule
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// 32-bit 8x1 mux
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module MUX32_8x1(Y, I0, I1, I2, I3, I4, I5, I6, I7, S);
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// output list
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output [31:0] Y;
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//input list
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input [31:0] I0;
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input [31:0] I1;
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input [31:0] I2;
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input [31:0] I3;
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input [31:0] I4;
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input [31:0] I5;
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input [31:0] I6;
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input [31:0] I7;
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input [2:0] S;
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// TBD
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endmodule
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// 32-bit 4x1 mux
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module MUX32_4x1(Y, I0, I1, I2, I3, S);
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// output list
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output [31:0] Y;
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//input list
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input [31:0] I0;
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input [31:0] I1;
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input [31:0] I2;
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input [31:0] I3;
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input [1:0] S;
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// TBD
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endmodule
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// 32-bit mux
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module MUX32_2x1(Y, I0, I1, S);
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// output list
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output [31:0] Y;
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//input list
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input [31:0] I0;
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input [31:0] I1;
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input S;
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// only need 1 not gate
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not (S_not, S);
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wire [31:0] x0, x1;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : mux32_gen_loop
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and (x0[i], S_not, I0[i]);
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and (x1[i], S, I1[i]);
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or (Y[i], x0[i], x1[i]);
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end
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endgenerate
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endmodule
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// 1-bit mux
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module MUX1_2x1(Y,I0, I1, S);
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//output list
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output Y;
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//input list
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input I0, I1, S;
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not (S_not, S);
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and (x0, S_not, I0);
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and (x1, S, I1);
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or (Y, x0, x1);
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endmodule
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