49 lines
1009 B
Verilog
49 lines
1009 B
Verilog
// Name: rc_add_sub_32.v
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// Module: RC_ADD_SUB_32
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//
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// Output: Y : Output 32-bit
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// CO : Carry Out
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//
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//
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// Input: A : 32-bit input
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// B : 32-bit input
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// SnA : if SnA=0 it is add, subtraction otherwise
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//
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// Notes: 32-bit adder / subtractor implementaiton.
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module RC_ADD_SUB_64(Y, CO, A, B, SnA);
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// output list
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output [63:0] Y;
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output CO;
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// input list
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input [63:0] A;
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input [63:0] B;
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input SnA;
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// TBD
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endmodule
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module RC_ADD_SUB_32(Y, CO, A, B, SnA);
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// output list
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output [`DATA_INDEX_LIMIT:0] Y;
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output CO;
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// input list
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input [`DATA_INDEX_LIMIT:0] A;
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input [`DATA_INDEX_LIMIT:0] B;
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input SnA;
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// TBD
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endmodule
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