87 lines
2.0 KiB
Verilog
87 lines
2.0 KiB
Verilog
// Name: mult_tb.v
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// Module: MULT_U_TB, MULT_TB
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//
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// Notes: - Testbench for multiplier
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module MULT_U_TB;
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// driver
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reg [`DATA_INDEX_LIMIT:0] A;
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reg [`DATA_INDEX_LIMIT:0] B;
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// outputs to observe
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wire [`DATA_INDEX_LIMIT:0] HI, LO;
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// result registers
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integer i;
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reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:4];
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MULT32_U mult32_u_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
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initial
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begin
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i=0;
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A=10; B=20; // Y = 10 * 20 = 200
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=3; B=15; // Y = 3 * 15 = 45
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=16; B=7; // Y = 16 * 7 = 112
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=10; B=19; // Y = 10 * 19 = 190
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=32'h70000000; B=32'h70000000;
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#1 result[i] = {HI,LO}; i=i+1;
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#1
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$writememh("./OUTPUT/mult32_u_tb.out", result);
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$stop;
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end
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endmodule
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module MULT_TB;
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// driver
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reg [`DATA_INDEX_LIMIT:0] A;
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reg [`DATA_INDEX_LIMIT:0] B;
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// outputs to observe
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wire [`DATA_INDEX_LIMIT:0] HI, LO;
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// result registers
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integer i;
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reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:7];
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MULT32 mult32_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
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initial
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begin
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i=0;
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A=10; B=20; // Y = 10 * 20 = 200
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=-3; B=-15; // Y = 3 * 15 = 45
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=-16; B=7; // Y = 16 * 7 = -112
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=10; B=-19; // Y = 10 * 19 = -190
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=32'h70000000; B=32'h70000000;
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=32'h90000000; B=32'h70000000;
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=32'h70000000; B=32'h90000000;
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#1 result[i] = {HI,LO}; i=i+1;
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#1 A=32'h90000000; B=32'h90000000;
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#1 result[i] = {HI,LO}; i=i+1;
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#1
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$writememh("./OUTPUT/mult32_tb.out", result);
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$stop;
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end
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endmodule
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