27 lines
600 B
Verilog
27 lines
600 B
Verilog
// Name: half_adder.v
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// Module: HALF_ADDER
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//
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// Output: Y : Sum
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// C : Carry
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//
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// Input: A : Bit 1
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// B : Bit 2
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//
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// Notes: 1-bit half adder implementaiton.
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module HALF_ADDER(Y,C,A,B);
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output Y,C;
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input A,B;
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// TBD
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endmodule; |