38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
// Name: alu.v
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// Module: ALU
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// Input: OP1[32] - operand 1
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// OP2[32] - operand 2
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// OPRN[6] - operation code
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// Output: OUT[32] - output result for the operation
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//
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// Notes: 32 bit combinatorial ALU
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//
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// Supports the following functions
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// - Integer add (0x1), sub(0x2), mul(0x3)
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// - Integer shift_rigth (0x4), shift_left (0x5)
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// - Bitwise and (0x6), or (0x7), nor (0x8)
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// - set less than (0x9)
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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module ALU(OUT, ZERO, OP1, OP2, OPRN);
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// input list
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input [`DATA_INDEX_LIMIT:0] OP1; // operand 1
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input [`DATA_INDEX_LIMIT:0] OP2; // operand 2
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input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
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// output list
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output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
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output ZERO;
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// TBD
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endmodule
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