61 lines
2.0 KiB
Verilog
61 lines
2.0 KiB
Verilog
// Name: control_unit.v
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// Module: CONTROL_UNIT
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// Output: CTRL : Control signal for data path
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// READ : Memory read signal
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// WRITE : Memory Write signal
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//
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// Input: ZERO : Zero status from ALU
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// CLK : Clock signal
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// RST : Reset Signal
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//
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// Notes: - Control unit synchronize operations of a processor
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// Assign each bit of control signal to control one part of data path
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
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// Output signals
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output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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output READ, WRITE;
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// input signals
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input ZERO, CLK, RST;
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input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
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// TBD - take action on each +ve edge of clock
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endmodule
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//------------------------------------------------------------------------------------------
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// Module: PROC_SM
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// Output: STATE : State of the processor
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//
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// Input: CLK : Clock signal
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// RST : Reset signal
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//
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// INOUT: MEM_DATA : Data to be read in from or write to the memory
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//
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// Notes: - Processor continuously cycle witnin fetch, decode, execute,
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// memory, write back state. State values are in the prj_definition.v
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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module PROC_SM(STATE,CLK,RST);
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// list of inputs
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input CLK, RST;
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// list of outputs
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output [2:0] STATE;
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// TBD - take action on each +ve edge of clock
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endmodule |