Yuri Tatishchev
cce0c524d9
Gate level implementation for the following components: - ALU - MUX32_16x1
169 lines
2.8 KiB
Verilog
169 lines
2.8 KiB
Verilog
// Name: logic.v
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// Module:
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// Input:
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// Output:
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//
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// Notes: Common definitions
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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// 64-bit two's complement
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module TWOSCOMP64(Y,A);
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//output list
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output [63:0] Y;
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//input list
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input [63:0] A;
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RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
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endmodule
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// 32-bit two's complement
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module TWOSCOMP32(Y,A);
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//output list
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output [31:0] Y;
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//input list
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input [31:0] A;
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RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
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endmodule
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// 32-bit registere +ve edge, Reset on RESET=0
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module REG32(Q, D, LOAD, CLK, RESET);
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output [31:0] Q;
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input CLK, LOAD;
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input [31:0] D;
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input RESET;
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// TBD
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endmodule
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// 1 bit register +ve edge,
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// Preset on nP=0, nR=1, reset on nP=1, nR=0;
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// Undefined nP=0, nR=0
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// normal operation nP=1, nR=1
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module REG1(Q, Qbar, D, L, C, nP, nR);
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input D, C, L;
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input nP, nR;
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output Q,Qbar;
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wire D_out;
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MUX1_2x1 data(D_out, Q, D, L);
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D_FF dff(Q, Qbar, D_out, C, nP, nR);
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endmodule
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// 1 bit flipflop +ve edge,
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// Preset on nP=0, nR=1, reset on nP=1, nR=0;
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// Undefined nP=0, nR=0
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// normal operation nP=1, nR=1
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module D_FF(Q, Qbar, D, C, nP, nR);
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input D, C;
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input nP, nR;
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output Q,Qbar;
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wire Cbar, Y, Ybar;
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not C_inv(Cbar, C);
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D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
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SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
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endmodule
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// 1 bit D latch
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// Preset on nP=0, nR=1, reset on nP=1, nR=0;
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// Undefined nP=0, nR=0
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// normal operation nP=1, nR=1
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module D_LATCH(Q, Qbar, D, C, nP, nR);
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input D, C;
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input nP, nR;
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output Q,Qbar;
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wire Dbar;
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not D_inv(Dbar, D);
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SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
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endmodule
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// 1 bit SR latch
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// Preset on nP=0, nR=1, reset on nP=1, nR=0;
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// Undefined nP=0, nR=0
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// normal operation nP=1, nR=1
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module SR_LATCH(Q,Qbar, S, R, C, nP, nR);
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input S, R, C;
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input nP, nR;
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output Q,Qbar;
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wire r1, r2;
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nand n1(r1, C, S);
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nand n2(r2, C, R);
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nand n3(Q, nP, r1, Qbar);
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nand n4(Qbar, nR, r2, Q);
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endmodule
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// 5x32 Line decoder
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module DECODER_5x32(D,I);
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// output
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output [31:0] D;
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// input
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input [4:0] I;
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// TBD
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endmodule
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// 4x16 Line decoder
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module DECODER_4x16(D,I);
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// output
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output [15:0] D;
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// input
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input [3:0] I;
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// TBD
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endmodule
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// 3x8 Line decoder
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module DECODER_3x8(D,I);
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// output
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output [7:0] D;
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// input
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input [2:0] I;
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//TBD
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endmodule
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// 2x4 Line decoder
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module DECODER_2x4(D,I);
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// output
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output [3:0] D;
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// input
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input [1:0] I;
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wire I_not [1:0];
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not I_inv[1:0] (I_not, I);
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and (D[0], I_not[1], I_not[0]);
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and (D[1], I_not[1], I[0]);
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and (D[2], I[1], I_not[0]);
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and (D[3], I[1], I[0]);
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endmodule
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