Yuri Tatishchev
cce0c524d9
Gate level implementation for the following components: - ALU - MUX32_16x1
87 lines
2.3 KiB
Verilog
87 lines
2.3 KiB
Verilog
// Name: alu.v
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// Module: ALU
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// Input: OP1[32] - operand 1
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// OP2[32] - operand 2
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// OPRN[6] - operation code
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// Output: OUT[32] - output result for the operation
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//
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// Notes: 32 bit combinatorial ALU
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//
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// Supports the following functions
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// - Integer add (0x1), sub(0x2), mul(0x3)
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// - Integer shift_rigth (0x4), shift_left (0x5)
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// - Bitwise and (0x6), or (0x7), nor (0x8)
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// - set less than (0x9)
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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module ALU(OUT, ZERO, OP1, OP2, OPRN);
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// input list
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input [`DATA_INDEX_LIMIT:0] OP1; // operand 1
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input [`DATA_INDEX_LIMIT:0] OP2; // operand 2
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input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
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// output list
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output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
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output ZERO;
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wire [31:0] res,
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res_addsub, res_slt,
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res_shift,
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res_mul,
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res_and, res_or, res_nor;
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// add = xx0001
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// sub = xx0010
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// slt = xx1001
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// ^ ^ these bits
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// can use oprn[1] or oprn[3] for SnA
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wire SnA;
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or (SnA, OPRN[1], OPRN[3]);
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RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
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buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
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// shift_r = xx0100
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// shift_l = xx0101
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// ^ this bit
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// can use oprn[0] for LnR
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SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
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// mul = xx0011
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MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
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// and = xx0110
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// or = xx0111
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// nor = xx1000
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AND32_2x1 and32(res_and, OP1, OP2);
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OR32_2x1 or32(res_or, OP1, OP2);
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NOR32_2x1 nor32(res_nor, OP1, OP2);
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MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
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.I1(res_addsub), .I2(res_addsub), .I3(res_mul),
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.I4(res_shift),.I5(res_shift),
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.I6(res_and), .I7(res_or), .I8(res_nor),
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.I9(res_slt)
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);
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// or bits of result for zero flag
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wire nzf [31:0];
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buf (nzf[0], res[0]);
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genvar i;
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generate
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for (i = 1; i < 32; i = i + 1) begin : zf_gen
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or (nzf[i], nzf[i-1], res[i]);
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end
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endgenerate
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not (ZERO, nzf[31]);
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buf res_out [31:0] (OUT, res);
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endmodule
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