CaZzzer

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• Joined on 2021-03-03

Repositories

11

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5

CaZzzer pushed to lab-06 at CaZzzer/cs147dv 2024-10-10 22:14:41 +00:00

800b80ef85 lab-06 (WIP): mux32_16x1 working

CaZzzer created branch lab-06 in CaZzzer/cs147dv 2024-10-10 22:14:41 +00:00

CaZzzer pushed to lab-05 at CaZzzer/cs147dv 2024-10-10 20:32:55 +00:00

585d9713d2 lab-05: gate level model for 32-bit barrel shifter

CaZzzer created branch lab-05 in CaZzzer/cs147dv 2024-10-10 20:32:55 +00:00

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 23:00:18 +00:00

cdfaa51626 lab-04: signed mult working

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 21:48:53 +00:00

73aa647c9b lab-04 (WIP): unsigned mult working

CaZzzer created branch lab-04 in CaZzzer/cs147dv 2024-10-08 07:08:07 +00:00

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 07:08:07 +00:00

6fa94cfe59 lab-04 (WIP): mux implementation

CaZzzer pushed to master at CaZzzer/cs147dv 2024-10-04 04:31:34 +00:00

597e245641 lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

42732e4fe0 lab-02: gate level model for ripple carry adder subtractor

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CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 04:14:41 +00:00

f4a3e3bb8b lab-03: clean up twos complement modules

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 04:13:49 +00:00

f5b19ae9fc lab-02: fix behavioral xor statement in RC_ADD_SUB modules

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 03:21:45 +00:00

48bdad0e8b lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-02 23:18:36 +00:00

bb7e172316 implement a Verilog gate level model for 64-bit Ripple Carry Adder and 32/64-bit twos complement

CaZzzer created branch lab-03 in CaZzzer/cs147dv 2024-10-02 23:18:36 +00:00

CaZzzer pushed to lab-02 at CaZzzer/cs147dv 2024-10-02 03:44:23 +00:00

3801d523de implement a Verilog gate level model for ripple carry adder subtractor

CaZzzer pushed to lab-02 at CaZzzer/cs147dv 2024-10-01 18:01:43 +00:00

d1475b5a4f implement a Verilog gate level model for ripple carry adder subtractor

CaZzzer created branch lab-02 in CaZzzer/cs147dv 2024-10-01 18:01:43 +00:00

CaZzzer created branch master in CaZzzer/cs147dv 2024-10-01 17:48:03 +00:00

CaZzzer pushed to master at CaZzzer/cs147dv 2024-10-01 17:48:03 +00:00

87e48f162e implement a Verilog gate level model for 32-bit basic logic gates

5520d6d716 initial commit

CaZzzer created repository CaZzzer/cs147dv 2024-10-01 17:47:40 +00:00