CaZzzer

0 Followers · 0 Following

• Joined on 2021-03-03

Repositories

11

Projects Packages Code Public Activity Starred Repositories

5

CaZzzer pushed to feature/monitoring at CaZzzer/alpina 2024-10-13 06:32:10 +00:00

30510c6690 WIP: containers dashboard - loki logs

c38f94f4ce WIP: monitoring improvements - containers dashboard

Compare 2 commits »

CaZzzer pushed to feature/monitoring at CaZzzer/alpina 2024-10-12 09:29:50 +00:00

002eb40b68 WIP: monitoring improvements

CaZzzer pushed to feature/monitoring at CaZzzer/alpina 2024-10-12 01:15:58 +00:00

6056add4d6 WIP: monitoring improvements

aaca0f94f8 monitoring: remove jaeger

97b812eb10 updates: nextcloud refactor to apache image instead of nginx

97d1db61d8 updates: postgres upgrade, data migration process

a8bc344aa2 updates: traefik to v3

Compare 7 commits »

CaZzzer pushed to feature/monitoring at CaZzzer/alpina 2024-10-12 01:08:59 +00:00

CaZzzer created branch feature/monitoring in CaZzzer/alpina 2024-10-12 01:08:59 +00:00

CaZzzer pushed to lab-06 at CaZzzer/cs147dv 2024-10-11 02:33:24 +00:00

8dbdebb9ce lab-06: gate level model for Arithmetic & Logic Unit

CaZzzer pushed to lab-06 at CaZzzer/cs147dv 2024-10-10 22:14:41 +00:00

800b80ef85 lab-06 (WIP): mux32_16x1 working

CaZzzer created branch lab-06 in CaZzzer/cs147dv 2024-10-10 22:14:41 +00:00

CaZzzer created branch lab-05 in CaZzzer/cs147dv 2024-10-10 20:32:55 +00:00

CaZzzer pushed to lab-05 at CaZzzer/cs147dv 2024-10-10 20:32:55 +00:00

585d9713d2 lab-05: gate level model for 32-bit barrel shifter

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 23:00:18 +00:00

cdfaa51626 lab-04: signed mult working

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 21:48:53 +00:00

73aa647c9b lab-04 (WIP): unsigned mult working

CaZzzer created branch lab-04 in CaZzzer/cs147dv 2024-10-08 07:08:07 +00:00

CaZzzer pushed to lab-04 at CaZzzer/cs147dv 2024-10-08 07:08:07 +00:00

6fa94cfe59 lab-04 (WIP): mux implementation

CaZzzer pushed to master at CaZzzer/cs147dv 2024-10-04 04:31:34 +00:00

597e245641 lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

42732e4fe0 lab-02: gate level model for ripple carry adder subtractor

Compare 2 commits »

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 04:14:41 +00:00

f4a3e3bb8b lab-03: clean up twos complement modules

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 04:13:49 +00:00

f5b19ae9fc lab-02: fix behavioral xor statement in RC_ADD_SUB modules

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-04 03:21:45 +00:00

48bdad0e8b lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement

CaZzzer created branch lab-03 in CaZzzer/cs147dv 2024-10-02 23:18:36 +00:00

CaZzzer pushed to lab-03 at CaZzzer/cs147dv 2024-10-02 23:18:36 +00:00

bb7e172316 implement a Verilog gate level model for 64-bit Ripple Carry Adder and 32/64-bit twos complement