lab-07: gate level model for 32-bit register

Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32

TESTBENCH/barrel_shifter_tb.v

@@ -18,7 +18,7 @@ reg LnR;
 wire [31:0] Y;
 
 integer reg_idx;
-reg [`DATA_INDEX_LIMIT:0] result[0:123];
+reg [`DATA_INDEX_LIMIT:0] result[0:63];
 
 integer i, e;
 integer no_of_test=0;
@@ -33,7 +33,7 @@ D=32'ha5a5a5a5;
 S=32'h00000000;
 LnR=1'b1; // left shift
 
-for(i=1; i<63; i=i+1)
+for(i=1; i<33; i=i+1)
 begin
 #5 
 no_of_test = no_of_test + 1;
@@ -51,7 +51,7 @@ end
 
 #5 LnR=1'b0; // right shift
 
-for(i=1; i<63; i=i+1)
+for(i=1; i<33; i=i+1)
 begin
 #5 
 no_of_test = no_of_test + 1;

alu.v

@@ -31,12 +31,11 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;
 
-wire [31:0] //res,
+wire [31:0] res,
             res_addsub, res_slt,
             res_shift,
             res_mul,
             res_and, res_or, res_nor;
-wire [31:0] res;
 
 // add = xx0001
 // sub = xx0010
@@ -72,10 +71,16 @@ MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
 );
 
 // or bits of result for zero flag
-wire nzf;
+wire nzf [31:0];
-or (nzf, res[24:0]);
+buf (nzf[0], res[0]);
+genvar i;
+generate
+    for (i = 1; i < 32; i = i + 1) begin : zf_gen
+        or (nzf[i], nzf[i-1], res[i]);
+    end
+endgenerate
 
-not (ZERO, nzf);
+not (ZERO, nzf[31]);
 buf res_out [31:0] (OUT, res);
 
 endmodule

barrel_shifter.v

@@ -22,14 +22,20 @@ input [31:0] S;
 input LnR;
 
 // check if upper bits are nonzero
-wire oob;
+wire oob [31:5];
-or (oob, S[31:5]);
+buf (oob[5], S[5]);
+genvar i;
+generate
+    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
+        or (oob[i], oob[i-1], S[i]);
+    end
+endgenerate
 
 wire [31:0] shifted;
 BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
 
 // return 0 if S >= 32
-MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob);
+MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
 
 endmodule
 

logic.v

@@ -43,7 +43,12 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-// TBD
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1) begin : reg_gen
+        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
+    end
+endgenerate
 
 endmodule
 
@@ -56,7 +61,10 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire D_out;
+MUX1_2x1 data(D_out, Q, D, L);
+
+D_FF dff(Q, Qbar, D_out, C, nP, nR);
 
 endmodule
 
@@ -69,7 +77,11 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire Cbar, Y, Ybar;
+not C_inv(Cbar, C);
+D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
+
+SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
 
 endmodule
 
@@ -82,7 +94,10 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire Dbar;
+not D_inv(Dbar, D);
+
+SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
 
 endmodule
 
@@ -95,7 +110,13 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;
 
-// TBD
+wire r1, r2;
+
+nand n1(r1, C, S);
+nand n2(r2, C, R);
+
+nand n3(Q, nP, r1, Qbar);
+nand n4(Qbar, nR, r2, Q);
 
 endmodule