CaZzzer/cs147dv
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
2 Commits 11 Branches 0 Tags
87e48f162ef0ed72ca156be118d68ba42ea4afc1
Commit Graph
2 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
CaZzzer 87e48f162e implement a Verilog gate level model for 32-bit basic logic gates 
Gate level implementation for the following components:
- NOR32_2x1
- AND32_2x1
- INV32_1x1
- OR32_2x1
 2024-10-01 10:44:45 -07:00
CaZzzer 5520d6d716 initial commit 2024-10-01 10:39:56 -07:00